Singapore, Singapore

Vaiyapuri Venkateshwaran

This inventor holds 3 USPTO granted patents. Top assignee: Texas Instruments Corporation. Active years: 2001-2002.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Vaiyapuri Venkateshwaran. Retrieved from https://idiyas.com/inventor/vaiyapuri-venkateshwaran

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 2.0

ph-index = 3

Forward Citations = 494(Granted Patents)


Company Filing History:


Years Active: 2001-2002

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3 patents (USPTO):Explore Patents

Title: Vaiyapuri Venkateshwaran and Semiconductor Packaging Innovations.

Introduction

Vaiyapuri Venkateshwaran is an inventor associated with semiconductor packaging innovations. Based in Singapore, he is credited with 3 patents and works at Texas Instruments.

Latest Patents

Among Venkateshwaran’s listed patents is “Multichip semiconductor assembly.” The invention describes a semiconductor chip stack with two chips and a leadframe positioned between them. Solder-ball connections link the chips’ input/output contact pads to the leadframe, with some leads shared between the chips.

Another listed patent is “Stacked flip-chip integrated circuit assemblage.” It describes multiple integrated-circuit dies attached to a substrate, with a larger chip positioned over a smaller chip or chips. Bumped terminals connect the dies to substrate pads and provide interconnections to external contacts.

Career Highlights

Venkateshwaran’s listed work focuses on multichip assemblies and stacked flip-chip arrangements. These approaches address how integrated circuits can be interconnected and packaged in compact configurations.

Collaborations

His listed coworker is Ji Cheng Yang. Their names are associated with semiconductor packaging work.

Conclusion

Vaiyapuri Venkateshwaran’s patent portfolio reflects contributions to stacked-chip and multichip semiconductor assembly, with an emphasis on interconnections and packaging design.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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