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For the Inventor, By the Inventor

Hyogo, Japan

Toshifumi Kobayashi

This inventor holds 16 USPTO granted patents. Top assignees: Mitsubishi Denki Kabushiki Kaisha, Renesas Technology Corp.. Active years: 1987-2004.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Toshifumi Kobayashi. Retrieved from https://idiyas.com/inventor/toshifumi-kobayashi

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 16

% Patents Active = 87.5

Average Co-Inventor Count = 1.9

ph-index = 10

Forward Citations = 249(Granted Patents)


Location History:

  • Itama, JP (1987)
  • Itami, JP (1988 - 1991)
  • Hyogo, JP (1987 - 1996)
  • Tokyo, JP (2003 - 2004)

Company Filing History:

goldMedal15 out of 21,351 
 
Mitsubishi Denki Kabushiki Kaisha
 patents
silverMedal1 out of 3,781 
 
Renesas Technology Corp.
 patents

Years Active: 1987-2004

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16 patents (USPTO):Explore Patents
1. 6777981 - Level shifting circuit (2004-08-17),
2. 6670841 - Level shifting circuit (2003-12-30),
3. 5481496 - Semiconductor memory device and method of data transfer therefor (1996-01-02),
4. 5146300 - Semiconductor integrated circuit device having improved stacked (1992-09-08),
5. 5130945 - Content addressable memory combining match comparisons of a plurality of (1992-07-14),
6. 5126968 - Content addressable semiconductor memory device and operating method (1992-06-30),
7. 4998027 - Arbiter circuit (1991-03-05),
8. 4982370 - Shared sense amplifier semiconductor memory (1991-01-01),
9. 4965767 - Associative memory having simplified memory cell circuitry (1990-10-23),
10. 4962379 - Arbiter circuit for processing concurrent requests for access to shared (1990-10-09),
11. 4924220 - Arbiter circuit for processing concurrent requests for access to shared (1990-05-08),
12. 4901282 - Power efficient static-column DRAM (1990-02-13),
13. 4818904 - Power on reset pulse generating circuit sensitive to rise time of the (1989-04-04),
14. 4731761 - Semiconductor memory (1988-03-15),
15. 4689770 - Semiconductor memory device (1987-08-25),

Title: The Innovations of Toshifumi Kobayashi

Introduction

Toshifumi Kobayashi is a notable inventor based in Hyogo, Japan. He has made significant contributions to the field of electronics, particularly in the development of level shifting circuits. With a total of 16 patents to his name, Kobayashi's work has had a considerable impact on the industry.

Latest Patents

Kobayashi's latest patents include innovative designs for level shifting circuits. One of his patents describes a level shifting circuit that features a charging means consisting of a charging regulator circuit. This circuit charges a second node to a logic "H" by setting a second switching circuit to an ON state and subsequently returns the second switching circuit to an OFF state when a first node changes from a logic "H" to a logic "L" due to an input signal change. Another patent outlines a level shifting circuit that includes discharging means made up of high-voltage N-type transistors, which are biased at predetermined voltages. This design enhances the efficiency and reliability of electronic devices.

Career Highlights

Throughout his career, Kobayashi has worked with prominent companies such as Mitsubishi Electric Corporation and Renesas Technology Corporation. His experience in these organizations has allowed him to refine his skills and contribute to groundbreaking technologies in the electronics sector.

Collaborations

Kobayashi has collaborated with esteemed colleagues, including Masaaki Mihara and Takeshi Hamamoto. These partnerships have fostered a creative environment that has led to the development of innovative solutions in their field.

Conclusion

Toshifumi Kobayashi's contributions to the field of electronics through his patents and collaborations highlight his role as a significant inventor. His work continues to influence the industry and inspire future innovations.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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