Content addressable semiconductor memory device and operating method

Abstract

A semiconductor memory device comprises a plurality or CAM cells. In a refreshing operation, data of '1' is applied to all of bit lines and inversion bit lines. In the CAM cells storing the data '1', writing of the data '1' onto the bit lines and the inversion bit lines is performed. Then, the data of '0' is applied to all of the bit lines and the inversion bit lines. In the CAM cells storing the data '0', writing of the data '0' onto the bit lines and the inversion bit lines is performed. In a partial writing operation, in the CAM cells to which writing is performed, a first control node is activated, thereby making it possible to write the CAM cells. In the rest of the CAM cells, the first control node is inactivated, thereby making it impossible to write the CAM cells.