Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Toshifumi Kobayashi

Masaaki Mihara

Takeshi Hamamoto

Michihiro Yamada

Koichiro Mashiko

Hiroshi Miyamoto

Tadato Yamagata

Yoshikazu Morooka

Kazutami Arimoto

Kenichi Yasuda

Mitsuya Kinoshita

Noriaki Matsumoto

A level shifting circuit includes a charging means consisting of a charging regulator circuit which charges a second node to a logic &ldquo;H&rdquo; by setting a second switching circuit to an ON state and thereafter brings back the second switching circuit to an OFF state when a first node is changed from a logic &ldquo;H&rdquo; to a logic &ldquo;L&rdquo; by a change of an input signal, and charges the first node to the logic &ldquo;H&rdquo; by setting a first switching circuit to the ON state and thereafter brings back the first switching circuit to the OFF state when the second node is changed from the logic &ldquo;H&rdquo; to the logic &ldquo;L&rdquo; by the change of the input signal.

Level shifting circuit

A level shifting circuit includes discharging means made up of a first high-voltage N-type transistor and a second high-voltage N-type transistor whose gates are biased respectively in a predetermined voltage and whose drains are connected to a first and second nodes respectively; and a first low-voltage N-type transistor and a second low-voltage N-type transistor whose drains are connected to sources of the first and second high-voltage N-type transistors respectively, whose gates are connected to the complementary input signal and whose sources are grounded respectively, and the predetermined voltage is set to an intermediate voltage between a threshold voltage of the first and second high-voltage N-type transistors and a breakdown voltage of the first and second low-voltage N-type transistors.

Sense amplifiers provided for each of the bit line pairs are divided into groups to be independently driven, whereby the influence of sense amplifiers of different groups can be prevented, and therefore the destruction of data of the non-selected memory cells during data transfer can be prevented. In transferring data from the data register to the memory cell array, the sense amplifier is not activated until the stored information of the memory cells selected by the word line is fully read to the corresponding bit lines, whereby the destruction of data stored in the non-selected memory cells can be prevented.

Semiconductor memory device and method of data transfer therefor

A semiconductor integrated circuit device including a semiconductor substrate having a main surface; a first conductive region formed on the main surface; a second conductive region formed on the main surface, spaced apart from the first conductive region and to be electrically connected to the first conductive region; and a capacitor having a storage node connecting the first and second conductive regions. The storage node serves to connect the first and second conductive regions and simultaneously stores charges. In other aspects of the invention, there are provided a memory cell having a structure described above, and a method of manufacturing the above-described semiconductor integrated circuit device.

Semiconductor integrated circuit device having improved stacked

Each match line is connected to a plurality of CAM cells constituting a CAM array. The respective CAM cells store data applied through a bit line and an inverted-bit line in its data storage portion when selected by a word line. The stored data are applied to a data comparison portion to be compared with retrieval data applied through the bit line and the inverted-bit line, thereby detecting match or mismatch therebetween. A comparison result of the data comparison portion is first stored in a capacitance element in the form of charge. In order to prevent escape of the information stored in the capacitance element, a blocking means blocks a part of a charge and discharge path for the capacitance element. A charge transfer means provided between the capacitance element and the match line transfers a certain amount of charge from either one to the other when information of mismatch is stored in the capacitance element. This causes fluctuation of charge potential on the match line. The fluctuation of potential on the match line depends on the number of mismatched CAM cells out of a plurality of CAM cells connected to the match line. Therefore, detection of potential on the match line permits detecting the number of mismatched CAM cells.

Content addressable memory combining match comparisons of a plurality of

A semiconductor memory device comprises a plurality or CAM cells. In a refreshing operation, data of '1' is applied to all of bit lines and inversion bit lines. In the CAM cells storing the data '1', writing of the data '1' onto the bit lines and the inversion bit lines is performed. Then, the data of '0' is applied to all of the bit lines and the inversion bit lines. In the CAM cells storing the data '0', writing of the data '0' onto the bit lines and the inversion bit lines is performed. In a partial writing operation, in the CAM cells to which writing is performed, a first control node is activated, thereby making it possible to write the CAM cells. In the rest of the CAM cells, the first control node is inactivated, thereby making it impossible to write the CAM cells.

Content addressable semiconductor memory device and operating method

Disclosed is an arbiter circuit for arbitrating a contention between two request signals which simultaneously attain the H (logical high) level indicating a 'request'. In this arbiter circuit, buffer circuits, having different input logic threshold voltages, are connected to the respective outputs of two three-input NAND gates. The respective outputs of these two buffer circuits, as signals indicating 'acknowledgement' or 'negative acknowledgement' of the request signals, are derived as final outputs of the arbiter circuit. One of the buffer circuits has an input logic threshold voltage lower than a logic threshold voltage of the two NAND gates, while the other buffer circuit has an input logic threshold voltage set higher than the logic threshold voltage of the NAND gates. Therefore, when the NAND gates output a voltage with the logic level neither the H level nor the L (logical low) level, a signal of the logic level H indicating the 'negative acknowledgement' and a signal of the logical level L indicating the 'acknowledgement' are reliably outputted from the buffer circuit with the lower input logic threshold voltage and from the other buffer circuit with the higher input logic threshold voltage, respectively. That is, even if two requests occur simultaneously, one of the request signals is rapidly acknowledged.

Arbiter circuit

In a dynamic random access semiconductor memory device comprising a sense amplifier and two pairs of bit lines sharing the sense amplifiers, each of the bit lines having a plurality of memory cells connected thereto, when a memory cell connected to one of the bit-line pairs is selected, the memory cells connected to the other bit-line pair are not connected to the sense amplifier, and, during a refresh cycle for rewriting data into a selected memory cell connected to a bit line of one of the bit-line pairs, the bit lines of the other bit-line pair are disconnected from the sense amplifier.

Shared sense amplifier semiconductor memory

A memory cell circuit of an associative memory composed of only four NMOS transistors is disclosed. Each memory cells of the circuit is connected two bit lines, a word line, a match setup line for commanding coincidence detection, and a match line for transferring the results of detection. The data signals are stored in the gate capacity of each of the transistors 3. This simplified memory cell circuit contributes to higher integration of the associative memory.

Associative memory having simplified memory cell circuitry

An arbiter circuit is disclosed for processing requests made at least two subsystems in a multiprocessor system for access to a resource shared by the subsystems. The arbiter circuit includes an SR flip-flop composed of a pair of NAND gates. The flip-flop is operative in response to a time-staggered request signals from the subsystems to provide a request acknowledging signal to the shared resource. When two request signals are simultaneously supplied to the arbiter circuit, the outputs from the pair of NAND gates tend to stay at an intermediate level between the normal two distincitive logic levels, failing to produce an acknowledgment signal. However, the intermediate level of the NAND gate outputs is sensed by a NOR gate to a trigger a switching device into conduction, by means of which one of the intermediate NAND gate outputs is positively shifted to either of the active logic levels for the generation of an acknowledgement signal to the shared resources. Thus, one of the two subsystems is allowed access to the shared resource.

Arbiter circuit for processing concurrent requests for access to shared

An arbiter circuit is disclosed for processing competing requests for access to a shared resource made simultaneously by two subsystems in a multi-processor system. The arbiter circuit includes an SR flip-flop composed of a pair of NAND gates, and functions to block the passage of a subsequent request signal from one subsystem to the SR flip-flop during a predetermined time interval after a request signal from the other subsystem has been supplied to the flip-flop. A result is that the both inputs of the SR flip-flop are not shifted up from the low levels to the high levels at the same time by the simultaneous generation of request signals from both subsystems, thereby eliminating any possibility of the output from the flip-flop floating at an intermediate level between the high and low level.

In a static column dynamic random access memory device in which memory operations including refresh operation are initiated responsive to a row address strobe signal, and the refresh operation for amplification and rewriting of information of the selected memory cell is not interrupted until its completion once it is started by the application of the row address strobe signal even if the row address strobe signal is thereafter removed; a timing circuit provides clocks for controlling the row circuits and the column circuit to cause termination of the memory operations if the row address strobe signal has been removed before the end of the refresh operation, and to cause continuation of the read/write memory operations if the row address strobe signal is still applied at the end of the refresh operation.

Power efficient static-column DRAM

A power on reset pulse generating circuit, which comprises a flip-flop coupled through capacitors to an applied supply voltage to be resettable thereby, a time constant circuit including an array of diode connecting MOS transistors and a capacitor coupled to reset the flip-flop in response to a fast rise time of an applied supply voltage, and another MOS transistor connected to detect a level of a voltage at the output terminal to reset the flip-flop in response to a slow rise time of the applied supply voltage.

Power on reset pulse generating circuit sensitive to rise time of the

A dynamic RAM with static column function comprising a predecoder for predecoding both the row address and the column address to output intermediate signals, a row decoder composed of NOR circuits for selecting one row in response to said intermediate signals, a column decoder composed of NAND circuits for selecting one column in response to said intermediate signals, and a logic inversion circuit for matching the logics for the intermediate signal between the row decoder and the column decoder.

Semiconductor memory

An LSI semiconductor memory device in which errors in reading out memory cells connected to outermost bit lines of a memory cell array of the device are substantially eliminated. In accordance with the invention, this is done by making capacitances associated with the bit lines of respective ones of the memory cell array substantially equal to one another. To accomplish this, the configuration of an inside portion of wiring other than the bit lines of the array is made the same as that of the bit lines, and the distance between the outermost bit line and the other wiring is made equal to the distance between adjacent ones of the bit lines.

Growing community of inventors

Hyogo, Japan

Toshifumi Kobayashi