Round Rock, TX, United States of America

Thomas E Spikes, Jr

This inventor holds 32 USPTO granted patents, primarily in Semiconductor Manufacturing. Top assignees: Advanced Micro Devices Corporation, Other. Active years: 1998-2003.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Thomas E Spikes, Jr. Retrieved from https://idiyas.com/inventor/thomas-e-spikes-jr

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 32

% Patents Active = 100.0

Average Co-Inventor Count = 2.9

ph-index = 10

Forward Citations = 318(Granted Patents)

Location History:

Round Park, TX (US) (2002)
Round Rock, TX (US) (1998 - 2003)

Company Filing History:

31 out of 13,168

Advanced Micro Devices Corporation

patents

1 out of 834,513

Other

patents

Years Active: 1998-2003

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Areas of Expertise:

MOSFET

Isolation Structure

Transistor

Gate Oxide

High Density Plasma

Salicidation

Trench Fill

Doping

Flash Memory

Interconnect

Spacer Structure

Wafer Cleaning

32 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 6599174 - Eliminating dishing non-uniformity of a process layer (2003-07-29),

2. 6555396 - Method and apparatus for enhancing endpoint detection of a via etch (2003-04-29),

3. 6458678 - Transistor formed using a dual metal process for gate and source/drain region (2002-10-01),

4. 6326251 - Method of making salicidation of source and drain regions with metal gate MOSFET (2001-12-04),

5. 6309936 - Integrated formation of LDD and non-LDD semiconductor devices (2001-10-30),

6. 6271112 - Interlayer between titanium nitride and high density plasma oxide (2001-08-07),

7. 6239476 - Integrated circuit isolation structure employing a protective layer and method for making same (2001-05-29),

8. 6228724 - Method of making high performance MOSFET with enhanced gate oxide integration and device formed thereby (2001-05-08),

9. 6225201 - Ultra short transistor channel length dictated by the width of a sidewall spacer (2001-05-01),

10. 6211000 - Method of making high performance mosfets having high conductivity gate conductors (2001-04-03),

11. 6194283 - High density trench fill due to new spacer fill method including isotropically etching silicon nitride spacers (2001-02-27),

12. 6171917 - Transistor sidewall spacers composed of silicon nitride CVD deposited from a high density plasma source (2001-01-09),

13. 6160316 - Integrated circuit utilizing an air gap to reduce capacitance between (2000-12-12),

14. 6140190 - Method and structure for elevated source/drain with polished gate (2000-10-31),

15. 6140163 - Method and apparatus for upper level substrate isolation integrated with (2000-10-31),

Title: The Innovative Journey of Thomas E. Spikes, Jr

Introduction:

Thomas E. Spikes, Jr, a talented inventor hailing from Round Rock, TX, has made significant contributions to the world of technology and innovation.

Latest Patents:

Thomas E. Spikes, Jr holds several patents in the field of electronics and telecommunications, showcasing his expertise and creativity in developing cutting-edge solutions.

Career Highlights:

With a career spanning over two decades, Thomas E. Spikes, Jr has worked with renowned tech companies, leading research institutions, and universities to bring his inventions to life. His dedication to pushing the boundaries of technology has earned him recognition in the industry.

Collaborations:

Throughout his career, Thomas E. Spikes, Jr has collaborated with top engineers, scientists, and researchers to enhance his inventions and bring them to the market. His collaborative spirit has led to groundbreaking innovations that have revolutionized the tech industry.

Conclusion:

In conclusion, Thomas E. Spikes, Jr's passion for innovation and his relentless pursuit of excellence have solidified his position as a prominent figure in the world of inventions. His contributions continue to inspire future generations of inventors and innovators.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]