Advanced Micro Devices Corporation

Other

Thomas E Spikes, Jr

Mark I Gardner

Robert Paiz

H Jim Fulford

Mark C Gilmer

Sey-Ping Sun

Robert Louis Dawson

Daniel Kadosh

Frederick N Hause

Fred N Hause

Mark W Michael

Anthony John Toprac

Jon D Cheek

Basab Bandyopadhyay

James F Buller

John A Iacoponi

David Donggang Wu

Michael P Duane

Tim Z Hossain

Craig William Christian

Allen Lewis Evans

Shyam G Garg

Derrick J Wristers

Christopher L Wooten

Nipendra J Patel

Ailian Zhao

A method includes providing at least one wafer having a process layer formed thereon. A surface of the process layer is polished using a first polishing process that is comprised of a slurry and a first polishing pad. The slurry is removed from the surface of the process layer. The surface of the process layer is planarized using a substantially slurryless second polishing process that is comprised of a second polishing pad that is more abrasive than the first polishing pad. A system includes a polishing tool and a process controller. The polishing tool is adapted to receive at least one wafer having a process layer formed thereon. The polishing tool is a adapted to polish a surface of the process layer using a first polishing process that is comprised of a slurry and a first polishing pad and remove the slurry from the surface of the process layer. The polishing tool is adapted to planarize the surface of the process layer using a substantially slurryless second polishing process that is comprised of a second polishing pad that is more abrasive than the first polishing pad. The process controller is coupled to the polishing tool and is adapted to communicate with at least one of a slurry controller and the polishing tool.

Eliminating dishing non-uniformity of a process layer

A method is provided to enhance endpoint detection during via etching in the processing of a semiconductor wafer. The method includes forming a first process layer and a second process layer above the first process layer. A first masking layer is formed above at least a portion of the second process layer, leaving an outer edge portion of at least the second process layer exposed. Thereafter, an etching process is used to remove the outer edge portion of the first and second layers. Once the etching is complete, the first masking layer is removed, and a second masking layer is formed above the second process layer. The second masking layer is patterned to expose portions of the first process layer, and then an etching process substantially removes the exposed portions of the first process layer to form the vias.

Method and apparatus for enhancing endpoint detection of a via etch

A method for forming a semiconductor device includes providing a substrate and forming a gate stack on the substrate. The gate stack includes a gate electrode having a thickness. Source/drain regions are formed in the substrate proximate the gate stack, and a first metal silicide layer is formed over the source drain regions. The thickness of the gate electrode is reduced, and a second metal silicide layer is formed over the reduced thickness gate electrode.

Transistor formed using a dual metal process for gate and source/drain region

A method of forming a transistor includes forming a source/drain implant in the initial processing stages just after the formation of the isolation and active regions on the substrate. A uniform nitride layer is formed over the surface of the substrate on top of a dielectric layer. A silicide metal is then deposited and reacted with the underlying silicon to form a salicide over the source and drain regions. A second dielectric layer is then formed on top of the salicide and is formed to be selective relative to the nitride layer. Thereafter, the nitride layer is removed and a final gate dielectric is then formed. Finally, a metal gate conductor is formed on top of the gate dielectric. The metal gate conductor is formed only after all annealing steps are performed to prevent the metal from spiking through the gate dielectric thereby ruining the device.

Method of making salicidation of source and drain regions with metal gate MOSFET

A method of forming a semiconductor device includes forming a first gate electrode over a substrate and then forming a spacer on at least one sidewall of the first gate electrode. A second gate electrode is formed over the substrate after forming the spacer. A first dopant is implanted into the substrate to form a first heavily doped active region adjacent to the spacer and spaced from the first gate electrode and a second heavily doped active region adjacent to the second gate electrode. The spacer is then removed and a second dopant is implanted into the substrate to form a lightly doped active region adjacent to the first gate electrode. In some instances, gate dielectrics for the first and second gate electrodes are formed using different materials and/or having different thicknesses.

Integrated formation of LDD and non-LDD semiconductor devices

A method for reducing die loss in a semiconductor fabrication process which employs titanium nitride and HDP oxide is provided. In the fabrication of multilevel interconnect structures, there is a propensity for defect formation in a process in which titanium nitride and HDP oxide layers are in contact along the edge of a semiconductor substrate. A dielectric interlayer is provided which improves the interfacial properties between titanium nitride and HDP oxide and thereby reduces defects caused by delamination at the titanium nitride/HDP oxide interface.

Interlayer between titanium nitride and high density plasma oxide

A method for fabricating an integrated circuit is presented wherein a trench is patterned in a field region of a semiconductor substrate. The trench is defined within the semiconductor substrate by a trench floor and trench sidewalls. A trench surface boundary is defined where the trench sidewalls intersect the upper surface of the semiconductor substrate. The trench may be filled with a trench fill material. A protective layer is then formed above the trench. The protective layer covers the trench and laterally extends above the semiconductor substrate at least a first distance beyond the trench surface boundaries.

Integrated circuit isolation structure employing a protective layer and method for making same

Transistors formed according to the present invention include an oxide layer/nitride layer gate insulator and a silicide gate conductor. An oxide layer is formed to a thickness of between 15 and 25 Angstroms across a substrate and partially removed so that a thickness of approximately 4 Angstroms remains. A nitride layer is formed upon oxide layer to a thickness of 10 to 20 Angstroms. Polysilicon gate conductors are then formed above the active regions of the substrate using a deposition and patterning technique. Spacers are then formed about the polysilicon gate conductor, lightly doped drain regions are formed and then source/drain regions are formed. In forming the lightly doped drain regions and the source/drain regions, the polysilicon gate conductor is doped. Then, a silicidation metal layer is deposited upon the polysilicon gate conductors and exposed portions of the nitride layer. The resultant structure is then subjected to an annealing step in which the polysilicon gate conductor is converted to a silicide gate conductor having a relatively lower bulk resistance. The remaining portions of the silicide metal layer are removed. Openings are then made to the source/drain regions through which interconnections are made to the transistor. A plurality of transistors formed according to this technique may be interconnected to form an integrated circuit.

Method of making high performance MOSFET with enhanced gate oxide integration and device formed thereby

An integrated circuit fabrication process is provided for forming a transistor having an ultra short channel length dictated by the width of a sidewall spacer which either embodies a gate conductor for the transistor or is used to pattern an underlying gate conductor. In one embodiment, the sidewall spacers are formed upon and extending laterally from the opposed sidewall surfaces of a sacrificial material. The sidewall surfaces of the sacrificial material are defined by forming the sacrificial material within an opening interposed laterally between vertically extending sidewalls which bound a gate dielectric. An upper portion of the gate dielectric is removed to partially expose the sidewall surfaces arranged at the periphery of the sacrificial material. Polysilicon spacers are formed exclusively upon the sidewall surfaces of the sacrificial material to define a pair of gate conductors having relatively small lateral widths. Portions of the gate dielectric not arranged exclusively beneath the gate conductors may be selectively removed. In another embodiment, sidewall spacers are used to protect select regions of a polysilicon gate material arranged exclusively underneath the spacers from being etched. The sidewall spacers are formed upon and extending laterally from sidewall surfaces arranged at the periphery of an opening which extends through a masking or sacrificial material to an underlying polysilicon gate material. The sidewall spacers are sacrificial in that they are removed from the semiconductor topography after they have served their purpose of masking the underlying polysilicon gate material.

Ultra short transistor channel length dictated by the width of a sidewall spacer

A method of fabricating an integrated circuit includes forming a gate stack upon an active region of a substrate which includes a gate dielectric, a polysilicon gate conductor and a polysilicon consumption metal layer portion. The polysilicon consumption metal layer portion is then reacted with the polysilicon gate conductor to form a high conductivity gate conductor (silicide). In one embodiment, the polysilicon gate conductor is fully consumed. In another embodiment, the polysilicon gate conductor is substantially consumed but a portion of the polysilicon gate conductor adjacent the gate dielectric remains. In forming such a gate structure, a gate dielectric layer is first formed and a polysilicon gate layer is formed upon the gate dielectric layer. A polysilicon consumption metal layer is then formed upon the polysilicon gate layer. The surface is then patterned mask so that the location of the gate structures is protected. The substrate is then anisotropically etched to form the gate structures. At this point, an optional rapid thermal annealing step may be performed to partially react the polysilicon consumption metal layer portion with the polysilicon gate conductor. Spacers, lightly doped drain regions and source and drain regions are then formed. Next, a silicidation metal layer is formed and the structure is reacted in a rapid thermal annealing step to form silicidation layers in the source and drain regions and to complete reaction of the polysilicon consumption metal layer portion with the gate conductor. Subsequently, the transistors may be interconnected to form an integrated circuit.

Method of making high performance mosfets having high conductivity gate conductors

A method for forming an isolation trench in a semiconductor substrate that is substantially free of voids. The method includes forming a dielectric masking layer above a semiconductor substrate. An opening is preferably formed through the masking layer and partially into the semiconductor substrate forming a shallow trench within the semiconductor substrate. Optionally, thermal oxidation of the trench may be performed to form an oxide layer within the trench. A spacer layer is preferably deposited across the exposed surface of the topography. The spacer layer is preferably etched to form spacers directly adjacent to opposed sidewall surfaces of the trench. The isolation trench may then be filled with an isolation dielectric. The presence of the spacers within the isolation trench preferably causes the lower portions of the trench to fill up faster than the upper portions. In this manner the trench may be filled without the formation of voids.

High density trench fill due to new spacer fill method including isotropically etching silicon nitride spacers

A method is provided for forming high quality nitride sidewall spacers laterally adjacent to the opposed sidewall surfaces of a gate conductor dielectrically spaced above a semiconductor substrate. In an embodiment, a polysilicon gate conductor is provided which is arranged between a pair of opposed sidewall surfaces upon a gate dielectric. The gate dielectric is arranged upon a semiconductor substrate. Nitride is deposited from a high density plasma source across exposed surfaces of the substrate and the gate conductor. The high density plasma source may be generated within an ECR or ICP reactor containing a gas bearing N,and SiH,. The energy and flux of electrons, ions, and radicals within the plasma are strictly controlled by the magnetic field such that a substantially stoichiometric and contaminant-free nitride is deposited upon the semiconductor topography. Thereafter, the nitride is anisotropically etched so as to form nitride spacers laterally adjacent the sidewall surfaces of the gate conductor.

Transistor sidewall spacers composed of silicon nitride CVD deposited from a high density plasma source

A method is provided for forming a multi-level interconnect in which capacitive coupling between laterally adjacent conductors employed by an integrated circuit is reduced. According to an embodiment, a conductor is dielectrically spaced above a semiconductor substrate, and a masking structure is arranged upon an upper surface of the conductor. Select portions of the conductor are removed such that opposed ends of the masking structure extend beyond opposed sidewall surfaces of the conductor. An interlevel dielectric is deposited to a level above the masking structure such that air gaps are formed laterally adjacent the opposed sidewall surfaces of the conductor, and the interlevel dielectric is planarized to a level spaced above an upper surface of the masking structure.

Integrated circuit utilizing an air gap to reduce capacitance between

A high performance semiconductor device structure and method of making the same include a bulk semiconductor substrate and an upper level silicon substrate. The upper level silicon substrate includes a low-K dielectric layer and a silicon substrate layer. The low-K dielectric layer is formed on the bulk semiconductor substrate, the low-K dielectric layer having a dielectric K-value in the range of 2.0-3.8. The silicon substrate layer and low-K dielectric layer are then patterned into the upper level substrate in a first region and the bulk semiconductor substrate is exposed in a second region. A gate oxide layer is formed over the upper level substrate in the first region and over the exposed bulk semiconductor substrate in the second region. Lastly, transistor device formations are formed in the upper level substrate and in the bulk semiconductor substrate.

Method and apparatus for upper level substrate isolation integrated with

A method and structure are provided for an IGFET which has elevated source/drain regions and polished gate electrode. The IGFET provides raised doped polysilicon regions between the source/drain areas and subsequent metallization layers. The doped polysilicon regions are scalable. Integration of elevated source/drain regions provides a shallow junction for high performance IGFET design. A refractory metal gate is provided without sacrificing the fabrication advantage of self-aligned techniques. A method to produce an IGFET which incorporates both of the above advantages into a single device, with relatively few process steps, is also provided. Fabricating the gate electrode in this manner will enable metal gate electrodes to be integrated with source/drain structure.

Growing community of inventors

Round Rock, TX, United States of America

Thomas E Spikes, Jr