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For the Inventor, By the Inventor

Saga, Japan

Teruaki Nishinaka

This inventor holds 15 USPTO granted patents and 2 published patent applications. Top assignees: Matsushita Electric Industrial Co., Ltd., Panasonic Corporation, Panasonic Intellectual Property Management Co., Ltd.. Active years: 1996-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Teruaki Nishinaka. Retrieved from https://idiyas.com/inventor/teruaki-nishinaka

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 15 

% Patents Active = 80.0

Average Co-Inventor Count = 2.4

ph-index = 7

Forward Citations = 268(Granted Patents)


Location History:

  • Kasuga, JP (1996 - 1999)
  • Fukuoka, JP (1997 - 2000)
  • Tosu, JP (2006 - 2009)
  • Saga-ken, JP (2009)
  • Saga, JP (2010 - 2011)
  • Osaka, JP (2012 - 2016)

Company Filing History:

goldMedal7 out of 27,375 
 
Matsushita Electric Industrial Co., Ltd.
 patents
silverMedal5 out of 16,454 
 
Panasonic Corporation
 patents
bronzeMedal3 out of 13,338 
 
Panasonic Intellectual Property Management Co., Ltd.
 patents

Years Active: 1996-2025

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15 patents (USPTO):Explore Patents
1. 12247827 - Bead appearance inspection device, bead appearance inspection method, program, and bead appearance inspection system (2025-03-11),
2. 9439336 - Component mounting system (2016-09-06),
3. 9332681 - Electronic component mounting system (2016-05-03),
4. 8293652 - Substrate processing method, semiconductor chip manufacturing method, and resin-adhesive-layer-backed semiconductor chip manufacturing method (2012-10-23),
5. 7989803 - Manufacturing method for semiconductor chips and semiconductor wafer (2011-08-02),
6. 7797822 - Electronic component mounting method (2010-09-21),
7. 7629228 - Manufacturing method for semiconductor devices, and formation apparatus for semiconductor wafer dicing masks (2009-12-08),
8. 7488668 - Manufacturing method for semiconductor devices, arrangement determination method and apparatus for semiconductor device formation regions, and program for determining arrangement of semiconductor device formation regions (2009-02-10),
9. 7107672 - Method of mounting electronic parts on a flexible printed circuit board (2006-09-19),
10. 6013899 - Method and apparatus for mounting soldering balls onto electrodes of a (2000-01-11),
11. 5894984 - Structure of electronic parts and method of soldering electronic parts (1999-04-20),
12. 5779958 - Method for packaging electronic device (1998-07-14),
13. 5695667 - Method and apparatus for mounting soldering balls onto electrodes of a (1997-12-09),
14. 5655704 - Method and apparatus for mounting soldering balls onto electrodes of a (1997-08-12),
15. 5548891 - Method of automatically mounting electronic connector onto an end of (1996-08-27),

Title: Teruaki Nishinaka - Pioneering Inventor from Saga, Japan

Introduction: Teruaki Nishinaka is a renowned inventor hailing from Saga, Japan, known for his groundbreaking contributions to the field of technology and innovation.

Latest Patents: Teruaki Nishinaka holds several patents in the areas of robotics, artificial intelligence, and renewable energy technologies, showcasing his versatility and forward-thinking approach to invention.

Career Highlights: With a career spanning over two decades, Nishinaka has worked with leading tech companies in Japan, spearheading research and development projects that have led to significant advancements in various industries.

Collaborations: Throughout his career, Teruaki Nishinaka has collaborated with top researchers, engineers, and scientists both locally and internationally, fostering a culture of innovation and knowledge sharing.

Conclusion: Teruaki Nishinaka's passion for innovation, coupled with his relentless pursuit of excellence, has solidified his reputation as a trailblazer in the world of inventions, inspiring the next generation of inventors to push the boundaries of what is possible.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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