The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7488668 B1

PDF
Full Text
Expired
Date of Patent:
Feb. 10, 2009

Filed:

Jul. 19, 2005
Applicants:

Kiyoshi Arita, Fukuoka-ken, JP;

Hiroshi Haji, Fukuoka-ken, JP;

Kazuhiro Noda, Fukuoka-ken, JP;

Akira Nakagawa, Saga-ken, JP;

Teruaki Nishinaka, Saga-ken, JP;

Inventors:

Kiyoshi Arita, Fukuoka-ken, JP;

Hiroshi Haji, Fukuoka-ken, JP;

Kazuhiro Noda, Fukuoka-ken, JP;

Akira Nakagawa, Saga-ken, JP;

Teruaki Nishinaka, Saga-ken, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 23/544 (2006.01);
U.S. Cl.
CPC ...
Abstract

With use of a length-dimension of a second-line-segment of a unit-device-formation-region as an arrangement interval, a plurality of parallel lines are disposed in a device-formation-effective-region on a wafer so as to form a plurality of parallel-line-partition-regions, the unit-device-formation-regions are arranged in each of the parallel-line-partition-regions independently of and separately from other parallel-line-partition-regions so that the acquisition number of the unit-device-formation-regions is maximized, and an arrangement of the respective unit-device-formation-regions in the respective parallel-line-partition-regions is determined as an arrangement of the entire device-formation-effective-region.


Find Patent Forward Citations

Arita, Kiyoshi. (2009). Manufacturing method for semiconductor devices, arrangement determination method and apparatus for semiconductor device formation regions, and program for determining arrangement of semiconductor device formation regions (U.S. Patent No. 7488668). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7488668

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…