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For the Inventor, By the Inventor

Machida, Japan

Takayuki Okamura

This inventor holds 15 USPTO granted patents, primarily in Semiconductor Memory. Top assignee: Kabushiki Kaisha Toshiba. Active years: 2010-2017.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Takayuki Okamura. Retrieved from https://idiyas.com/inventor/takayuki-okamura

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 15

% Patents Active = 33.3

Average Co-Inventor Count = 2.6

ph-index = 4

Forward Citations = 38(Granted Patents)


Location History:

  • Tokyo, JP (2010 - 2013)
  • Machida, JP (2010 - 2014)
  • Mie-ken, JP (2015)
  • Yokkaichi, JP (2014 - 2017)

Company Filing History:

goldMedal15 out of 53,286 
 
Kabushiki Kaisha Toshiba
 patents

Years Active: 2010-2017

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Areas of Expertise:
Semiconductor Device
Memory Device
Non-Volatile Memory
Resistance Change Memory
Manufacturing Method
Memory Technology
Electric Charge Layer
Laminated Gate
Memory Architecture
Device Fabrication
Integrated Circuit
Data Storage
15 patents (USPTO):Explore Patents
1. 9583629 - Semiconductor device (2017-02-28),
2. 9368196 - Semiconductor memory device (2016-06-14),
3. 9184217 - Memory device (2015-11-10),
4. 9142288 - Semiconductor memory device (2015-09-22),
5. 9111858 - Non-volatile semiconductor memory device and method for manufacturing the same (2015-08-18),
6. 8937830 - Semiconductor memory device (2015-01-20),
7. 8923031 - Semiconductor memory device (2014-12-30),
8. 8907318 - Resistance change memory (2014-12-09),
9. 8791552 - Semiconductor memory device and method for manufacturing the same (2014-07-29),
10. 8598649 - Nonvolatile semiconductor memory device and method for manufacturing same (2013-12-03),
11. 7960779 - Nonvolatile semiconductor memory and manufacturing method thereof (2011-06-14),
12. 7936005 - Semiconductor memory device including laminated gate having electric charge accumulating layer and control gate and method of manufacturing the same (2011-05-03),
13. 7872296 - Semiconductor memory device (2011-01-18),
14. 7795092 - Semiconductor device and manufacturing method thereof (2010-09-14),
15. 7737041 - Semiconductor device and method of manufacturing the same (2010-06-15),

Title: Takayuki Okamura: Innovator in Semiconductor Technology

Introduction

Takayuki Okamura is a prominent inventor based in Machida, Japan. He has made significant contributions to the field of semiconductor technology, holding a total of 15 patents. His work has been instrumental in advancing the capabilities of semiconductor devices and memory systems.

Latest Patents

Among his latest innovations, Okamura has developed a semiconductor device that features a first transistor with an asymmetrical structure. This device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a first gate insulating film, and a first gate electrode. The design allows for improved performance in semiconductor applications. Additionally, he has created a semiconductor memory device that comprises a memory cell array with memory cells configured to include a current rectifier element and a variable resistance element connected in series. This innovative design enhances the efficiency and functionality of memory systems.

Career Highlights

Okamura is associated with Kabushiki Kaisha Toshiba, a leading company in the technology sector. His work at Toshiba has allowed him to push the boundaries of semiconductor technology and contribute to the company's reputation for innovation.

Collaborations

Throughout his career, Okamura has collaborated with notable colleagues, including Nobuaki Yasutake and Jun Nishimura. These partnerships have fostered a collaborative environment that encourages the exchange of ideas and advancements in technology.

Conclusion

Takayuki Okamura's contributions to semiconductor technology are noteworthy and reflect his dedication to innovation. His patents and collaborations continue to influence the industry, making him a significant figure in the field.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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