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For the Inventor, By the Inventor

San Diego, CA, United States of America

Subbarao Palacharla

This inventor holds 26 USPTO granted patents and 26 published patent applications and 8 EPO patents, primarily in Memory Systems. Top assignee: Qualcomm Incorporated. Active years: 2016-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Subbarao Palacharla. Retrieved from https://idiyas.com/inventor/subbarao-palacharla

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 26 

% Patents Active = 61.5

 

Average Co-Inventor Count = 5.8

ph-index = 3

Forward Citations = 27(Granted Patents)


Company Filing History:

goldMedal26 out of 45,002 
 
Qualcomm Incorporated
 patents

Years Active: 2016-2026

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Areas of Expertise:
Autonomous Memory
Power Collapse
Process-in-Memory
Address Hashing
Error Handling
Adaptive Refresh
Memory Controller
Cache Replacement
Latency Reduction
Dynamic Metadata
Shared Cache
Multimedia Compression
26 patents (USPTO):Explore Patents
1. 12743142 - Autonomous memory power collapse (2026-09-22),
2. 12717726 - Process-in-memory (PIM)-aware address hashing (2026-08-25),
3. 12681800 - Freedom from interference (FFI) in electronics systems (2026-07-14),
4. 12640218 - Error handling for reprojection timeline (2026-05-26),
5. 12632398 - Memory system with adaptive refresh (2026-05-19),
6. 12625611 - Metadata registers for a memory device (2026-05-12),
7. 12620421 - Memory with reduced leakage through analog head switch control (2026-05-05),
8. 12541453 - Reconfigurable shared memory systems, and related processor-based systems and methods (2026-02-03),
9. 12487925 - Rank interleaving for system meta mode operations in a dynamic random access memory (DRAM) memory device (2025-12-02),
10. 12461860 - Physical address based set partitioning (2025-11-04),
11. 12307092 - Reducing latency in pseudo channel based memory systems (2025-05-20),
12. 12299283 - Self-characterizing, evaluating, and adaptive high performance memory controller (2025-05-13),
13. 12159033 - Metadata registers for a memory device (2024-12-03),
14. 12153531 - Multiple-core memory controller (2024-11-26),
15. 12038855 - Memory system with adaptive refresh (2024-07-16),

Title: Subbarao Palacharla: Innovator in Memory Systems

Introduction

Subbarao Palacharla is a prominent inventor based in San Diego, California. He has made significant contributions to the field of memory systems, holding a total of 16 patents. His work focuses on enhancing the efficiency and performance of memory subsystems in computing devices.

Latest Patents

Among his latest patents is a method for reducing latency in pseudo channel based memory systems. This invention includes various embodiments that feature devices designed to selectively connect multiple pseudo channels to input/output systems. Another notable patent is for a self-characterizing, evaluating, and adaptive high-performance memory controller. This system improves memory subsystem efficiency by detecting memory access events and adjusting operational parameters accordingly.

Career Highlights

Subbarao Palacharla is currently employed at Qualcomm Incorporated, a leading technology company known for its innovations in telecommunications and computing. His work at Qualcomm has allowed him to push the boundaries of memory technology, contributing to advancements that benefit a wide range of applications.

Collaborations

Throughout his career, Subbarao has collaborated with talented individuals such as Pankaj Deshmukh and Shyamkumar Thoziyoor. These collaborations have fostered an environment of innovation and creativity, leading to the development of cutting-edge technologies.

Conclusion

Subbarao Palacharla's contributions to memory systems exemplify the impact of innovative thinking in technology. His patents and work at Qualcomm continue to shape the future of computing.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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