Qualcomm Incorporated

Subbarao Palacharla

Jungwon Suh

Pankaj Deshmukh

Shyamkumar Thoziyoor

Alain Artieri

Kedar Bhole

George Patsilaras

Moinul H Khan

Vinod Chamarty

Raghu Sankuratri

Laurent Rene Moll

Yanru Li

Girish Bhat

Vipul Gandhi

Bohuslav Rychlik

Azzedine Touzni

Christopher E Koob

Andrew Edmund Turner

Simon Peter William Booth

Syed Minhaj Hassan

Hiral Nandu

Vishakh Balakuntalam Visweswara

Anurag Nannaka

Sparsh Singhai

Gopi Tummala

Jeong-Ho Woo

Jean-Jacques Lecler

Feng Wang

Anwar Q Rohillah

Michael Hawjing Lo

Samir Vijay Ginde

Olivier Alavoine

Jeffrey Shabel

Rakesh Kumar Gupta

Christophe Avoinne

Isaac Berk

Vikrant Kumar

Kris Tiri

Younghoon Kim

Tarek Zghal

Pankaj Chaurasia

Carlo Spitale

Hirai Nandu

Luigi Vinci

Sai Ramesh Bhyravajosula

Pavan Kumar Thirunagari

Yen-Kuan Wu

Zhenbiao Ma

Riccardo Iacobacci

This disclosure provides systems, methods, and devices for memory systems that support processing data and metadata within a memory of a memory device. In a first aspect, a method of controlling a memory device includes executing a first request in a first rank of the memory device during a first time period, wherein the first time period comprises a first data access portion and a first metadata access portion; and executing a second request in a second rank of the memory device during a second time period, wherein the second time period comprises a second data access portion and a second metadata access portion, wherein executing the first request in the first rank and executing the second request in the second rank comprises interleaving the first request and the second request between the first rank and the second rank. Other aspects and features are also claimed and described.

Rank interleaving for system meta mode operations in a dynamic random access memory (DRAM) memory device

Aspects presented herein relate to methods and devices for data or graphics processing including an apparatus, e.g., a graphics processing unit (GPU). The apparatus may configure an address range in a cache. The apparatus may also obtain a request to access data in the cache, where the request to access the data includes an address in the cache that maps to a set index in a plurality of set indexes, where an address value for the set index corresponds to a portion of the address. Further, the apparatus may select an updated address value for the set index, where the updated address value is associated with an updated address within the address range, and the updated address value corresponds to a portion of the updated address. The apparatus may also allocate the data in the request to the updated address value for the set index.

Physical address based set partitioning

Various embodiments include methods and devices for reducing latency in pseudo channel based memory systems. Embodiments may include a first pseudo channel selection device configured to selectively communicatively connect one of a plurality of pseudo channels to a first input/output (IO), and a second pseudo channel selection device configured to selectively communicatively connect one of the plurality of pseudo channels to a second IO, in which the first pseudo channel selection device and the second pseudo channel selection device may be operable to communicatively connect a first pseudo channel of the plurality of pseudo channels to the first IO and to the second IO concurrently. Embodiments may include the pseudo channel based memory system configured to receive a memory access command targeting the first pseudo channel, and use a first pseudo channel data bus and a second pseudo channel data bus to implement the memory access command.

Reducing latency in pseudo channel based memory systems

Various embodiments include systems and methods for improving the efficiency of a memory subsystem in a computing device. The memory subsystem may be configured to detect memory access events and determining their associated timings and determine an efficiency of the memory subsystem based on operational parameters of the memory subsystem, the detecting memory access events, and associated timings. The memory subsystem may adjust the operational parameters of the memory subsystem based on the determined efficiency of the memory subsystem. The memory subsystem may dynamically modify the operations of the memory subsystem based on the adjusted operational parameters.

Self-characterizing, evaluating, and adaptive high performance memory controller

This disclosure provides systems, methods, and devices for memory systems that support metadata. In a first aspect, a method of handling data and metadata at a memory device includes receiving data from the host via the at least one data connection into the first plurality of registers; receiving metadata from the host via the at least one non-data connection into the second plurality of registers; storing the data in the first portion of the memory array; and storing the metadata in the second portion of the memory array. Other aspects and features are also claimed and described.

Metadata registers for a memory device

This disclosure provides systems, methods, and devices for memory systems that support operating a least portions of a memory core at a frequency lower than a memory clock to reduce power consumption and cost. In a first aspect, a memory controller includes a first core for scheduling a first memory operation for a first portion of a clock cycle of the memory clock and includes a second core for scheduling a second memory operation for a second portion of the clock cycle of the memory clock. Other aspects and features are also claimed and described.

Multiple-core memory controller

A memory system with adaptive refresh commands is disclosed. In one aspect, a memory system or device that has multiple banks within a channel may receive a per bank command that indicates a first bank to be refreshed and provides additional information about a second bank to be refreshed. In a further exemplary aspect, a quad bank refresh command may be sent that indicates a first bank to be refreshed and provides additional information about second through fourth banks to be refreshed. In a further exemplary aspect, an octa bank refresh command may be sent that indicates a first bank to be refreshed and provides additional information about second through eighth banks to be refreshed. The three new refresh commands allow adjacent or spaced banks to be refreshed.

Memory system with adaptive refresh

Various embodiments include methods for implementing flexible ranks in a memory system. Embodiments may include receiving, at a memory controller, a first memory access command and a first address at which to implement the first memory access command in a logical rank, generating, by the memory controller, a first signal configured to indicate to a first memory device of the logical rank to implement the first memory access command via a first partial channel, sending, from the memory controller, the first signal to the first memory device, generating, by the memory controller, a second signal configured to indicate to a second memory device of the logical rank that is different from the first memory device to implement the first memory access command via a second partial channel, and sending, from the memory controller, the second signal to the second memory device.

Flexible dual ranks memory system to boost performance

Various embodiments include methods and devices for implementing a criterion aware cache replacement policy by a computing device. Embodiments may include updating a staling counter, writing a value of a local counter to a system cache in association with a location in the system cache for with data, in which the value of the local counter includes a value of the staling counter when (i.e., at the time) the associated data is written to the system cache, and using the value of the local counter of the associated data to determine whether the associated data is stale.

Multimedia compressed frame aware cache replacement policy

Integrated circuits (ICs) employ subsystem shared cache memory for facilitating extension of low-power island (LPI) memory. An LPI subsystem and primary subsystems access a memory subsystem on a first access interface in a first power mode and the LPI subsystem accesses the memory subsystem by a second access interface in the low power mode. In the first power mode, the primary subsystems and the LPI subsystem may send a subsystem memory access request including a virtual memory address to a subsystem memory interface of the memory subsystem to access either data stored in an external memory or a version of the data stored in a shared memory circuit. In the low-power mode, the LPI subsystem sends an LPI memory access request including a direct memory address to an LPI memory interface of the memory subsystem to access the shared memory circuit to extend the LPI memory.

Integrated circuits (IC) employing subsystem shared cache memory for facilitating extension of low-power island (LPI) memory and related methods

Data caching may include storing data associated with DRAM transaction requests in data storage structures organized in a manner corresponding to the DRAM bank, bank group and rank organization. Data may be selected for transfer to the DRAM by selecting among the data storage structures.

Dram-aware caching

Metadata is dynamically relocated in a DRAM from a virtual page that does not map to the same DRAM row in which the associated data is located, to that same DRAM row. If the target of a data access request is a location in a first page that is configured to store metadata rather than data, then a second location in a second page may be determined, and the requested data may be accessed at the second location. The associated metadata may be accessed at the location in the first page, which is configured in the virtual domain to store data but is configured in the physical domain to store the metadata associated with the data in the first page.

Dynamic metadata relocation in memory

Aspects include computing devices, systems, and methods for implementing a cache maintenance or status operation for a component cache of a system cache. A computing device may generate a component cache configuration table, assign at least one component cache indicator of a component cache to a master of the component cache, and map at least one control register to the component cache indicator by a centralized control entity. The computing device may store the component cache indicator such that the component cache indicator is accessible by the master of the component cache for discovering a virtualized view of the system cache and issuing a cache maintenance or status command for the component cache bypassing the centralized control entity. The computing device may receive the cache maintenance or status command by a control register associated with a cache maintenance or status command and the component cache bypassing the centralized control entity.

Method and apparatus for virtualized control of a shared system cache

Aspects include computing devices, systems, and methods for dynamically partitioning a system cache by sets and ways into component caches. A system cache memory controller may manage the component caches and manage access to the component caches. The system cache memory controller may receive system cache access requests and reserve locations in the system cache corresponding to the component caches correlated with component cache identifiers of the requests. Reserving locations in the system cache may activate the locations in the system cache for use by a requesting client, and may also prevent other client from using the reserved locations in the system cache. Releasing the locations in the system cache may deactivate the locations in the system cache and allow other clients to use them. A client reserving locations in the system cache may change the amount of locations it has reserved within its component cache.

Method and apparatus for a shared cache with dynamic partitioning

Growing community of inventors

San Diego, CA, United States of America

Subbarao Palacharla