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For the Inventor, By the Inventor

Fremont, CA, United States of America

Srinivas T Reddy

USPTO Granted Patents = 99

 

Average Co-Inventor Count = 3.9

ph-index = 33

Forward Citations = 3,156(Granted Patents)

DiyaCoin DiyaCoin = 1.42 


Inventors with similar research interests:


Location History:

  • Santa Clara, CA (US) (1994 - 2005)
  • Fremont, CA (US) (1998 - 2021)

Company Filing History:

goldMedal96 out of 4,283 
 
Altera Corporation
 patents
silverMedal1 out of 1 
 
Altera Corporation San Jose Ca
 patent
bronzeMedal1 out of 5,002 
 
Xilinx, Inc.
 patents
4. 1 out of 832,680 
Other
 patents

Years Active: 1994-2021

where 'Filed Patents' based on already Granted Patents

99 patents (USPTO):
1. 10977404 - Dynamic scan chain and method (2021-04-13),
2. 9208357 - FPGA configuration bitstream protection using multiple keys (2015-12-08),
3. 9094014 - PLD architecture for flexible placement of IP function blocks (2015-07-28),
4. 8826038 - FPGA configuration bitstream protection using multiple keys (2014-09-02),
5. 8732646 - PLD architecture for flexible placement of IP function blocks (2014-05-20),
6. 8407649 - PLD architecture for flexible placement of IP function blocks (2013-03-26),
7. 8209545 - FPGA configuration bitstream protection using multiple keys (2012-06-26),
8. 8201129 - PLD architecture for flexible placement of IP function blocks (2012-06-12),
9. 8198914 - Apparatus and methods for adjusting performance of programmable logic devices (2012-06-12),
10. 7936184 - Apparatus and methods for adjusting performance of programmable logic devices (2011-05-03),
11. 7725738 - FPGA configuration bitstream protection using multiple keys (2010-05-25),
12. 7620876 - Reducing false positives in configuration error detection for programmable devices (2009-11-17),
13. 7584447 - PLD architecture for flexible placement of IP function blocks (2009-09-01),
14. 7253660 - Multiplexing device including a hardwired multiplexer in a programmable logic device (2007-08-07),
15. 7236008 - Multiple size memories in a programmable logic device (2007-06-26),

Title: Innovator Spotlight: Srinivas T Reddy

Introduction: Srinivas T Reddy is a prolific inventor based in Fremont, CA (US) known for his groundbreaking work in the field of programmable integrated circuits and FPGA configuration security. With an impressive portfolio of 99 patents to his name, Reddy has made significant contributions to the technological landscape.

Latest Patents:

1. "Dynamic scan chain and method": Reddy's innovative approach involves dynamically creating scan chains in a programmable IC, enhancing circuit design efficiency.

2. "FPGA configuration bitstream protection using multiple keys": Reddy's patent focuses on preventing detection and erasure of encoding keys, ensuring data security in FPGA devices.

Career Highlights: Reddy has lent his expertise to renowned companies such as Altera Corporation, where he has spearheaded cutting-edge projects in San Jose, CA. His contributions have significantly impacted the development of programmable ICs and FPGA technology.

Collaborations: Reddy has worked closely with esteemed colleagues such as Richard G Cliff and Christopher F Lane, fostering a culture of innovation and collaboration within the teams he has been a part of.

Conclusion: Srinivas T Reddy stands out as a trailblazer in the field of inventions, with an impressive array of patents and a track record of success in driving technological advancements. His work continues to inspire and shape the future of programmable ICs and FPGA devices.

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