The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 03, 2011
Filed:
Feb. 24, 2006
Andy L. Lee, San Jose, CA (US);
Christopher F. Lane, San Jose, CA (US);
Ketan H. Zaveri, San Jose, CA (US);
Richard G. Cliff, Los Altos, CA (US);
Cameron R. Mcclintock, Mountain View, CA (US);
Srinivas T. Reddy, Fremont, CA (US);
David Lewis, Toronto, CA;
Andy L. Lee, San Jose, CA (US);
Christopher F. Lane, San Jose, CA (US);
Ketan H. Zaveri, San Jose, CA (US);
Richard G. Cliff, Los Altos, CA (US);
Cameron R. McClintock, Mountain View, CA (US);
Srinivas T. Reddy, Fremont, CA (US);
David Lewis, Toronto, CA;
Altera Corporation, San Jose, CA (US);
Abstract
A programmable logic device (PLD) includes at least two regions. Each region includes electrical circuitry that has a set of transistors. Each of the two regions has a corresponding fixed transistor threshold voltage, a corresponding fixed transistor body bias, and a corresponding fixed supply voltage.