Altera Corporation

Other

Xilinx, Inc.

Altera Corporation San Jose Ca

Srinivas T Reddy

Richard G Cliff

Christopher F Lane

David Edward Jefferson

Andy Louie Lee

Bruce B Pedersen

Cameron R McClintock

Manuel M Mejia

Ketan H Zaveri

David Lewis

Kerry S Veenstra

Joseph Huang

Rina Raman

Paul Leventis

Brian D Johnson

L Todd Cope

Vaughn Betz

Chiakang Sung

David Wolk Mendel

Francis B Heile

Bonnie I Wang

Keone Streicher

Chris Lane

Martin Langhammer

Craig S Lytle

Juju Joyce

Nitin Prasad

Anil Gupta

Fung Fung Lee

Andreas Papaliolios

Robert Richard Noel Bielby

James G Schleicher

Ninh D Ngo

Richard Shaw Terrill

Robert R Bielby

Vikram Santurkar

Chris Wysocki

Triet M Nguyen

Alexander Marquardt

Rakesh H Patel

Tony K Ngai

Dinesh D Gaitonde

Yi-Wen Lin

Michael Chan

Mario E Guzman

Bruce B Pederson

Changsong Zhang

Quyen Doan

Robert Blake

Ritesh Mani

Vaughn Timothy Betz

Cameron Mcclintock

Brian Johnson

Disclosed approaches for dynamically creating one or more scan chains in a programmable integrated circuit (IC) include placing elements of a circuit design on first registers of the programmable IC. A processor can determine second registers of the programmable IC that are unused by the circuit design after placing the elements of the circuit design. Data-out pins of the first registers are coupled to data-in pins of the second registers, respectively, and the second registers are coupled into a scan chain.

Dynamic scan chain and method

Circuits, methods, and apparatus that prevent detection and erasure of encoding or encryption keys. These encoding keys may be used to encode a configuration bitstream or other data for an FPGA or other device. An exemplary embodiment of the present invention masks a first key to form an encoding key in order to prevent detection of the first key. In a specific embodiment, the first key is encoded using a second key. The encoded key is used to encode a configuration bitstream or other data. The encoded key is stored on an FPGA or other device. When the device is to be configured, the encoded key is retrieved and used to decode the bitstream or other data. A further embodiment stores an encryption key in a one-time programmable memory (OTP) array to prevent its erasure or modification. The encoding key may be further obfuscated before storage.

FPGA configuration bitstream protection using multiple keys

In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.

PLD architecture for flexible placement of IP function blocks

A programmable logic device (PLD) includes at least two regions. Each region includes electrical circuitry that has a set of transistors. Each of the two regions has a corresponding fixed transistor threshold voltage, a corresponding fixed transistor body bias, and a corresponding fixed supply voltage.

Apparatus and methods for adjusting performance of programmable logic devices

A device reduces false positive memory error detections by using a masking unit and sensitivity mask data to exclude unused portions of the memory from the error detection computations. A device includes an error detection unit to read data from the memory and verify data integrity. The sensitivity mask data indicates unused portions of the memory. Unused portions of the memory may correspond with configuration data for unused portions of a programmable device. Each bit of the sensitivity mask data may indicate the usage of one or more bits of the data from the memory. In response to the mask data, the masking unit sets data from the unused portions of the memory to values that do not change the result of the error detection computations. This prevents any errors in data from the unused portions of the memory from raising an error signal.

Reducing false positives in configuration error detection for programmable devices

A multiplexing device is described. In one embodiment, the multiplexing device includes: a hardwired multiplexer including a plurality of input terminals; a plurality of select terminals; and at least one output terminal, where the plurality of input terminals are coupled to a plurality of block input lines or a plurality of functional element input terminals. In one embodiment, the plurality of input terminals are hardwired to the plurality of block input lines or the plurality of functional element input terminals. In one embodiment, the plurality of select terminals are coupled to a second plurality of functional element input terminals or a plurality of functional element output terminals. In one embodiment, the plurality of block input lines include a plurality of logic array block (LAB) lines, the plurality of functional element input terminals include a plurality of logic element (LE) input terminals, and the plurality of functional element output terminals include LE output terminals. In another embodiment the multiplexing device includes: a hardwired multiplexer including a plurality of data signal input terminals; and a first plurality of LEs including a first plurality of LE output terminals, where the plurality of data signal input terminals are coupled to the first plurality of LE output terminals.

Multiplexing device including a hardwired multiplexer in a programmable logic device

Circuits, methods, and apparatus that provide integrated circuits having memories with multiple sizes. The memories may be dedicated embedded memories, or they may be distributed memories formed using memories or lookup tables in logic elements or other appropriate circuits. Configuration bits not needed by logic elements used for distributed memories can be used for data storage as well. These various memories may be combined or otherwise linked or chained together in different combinations to form larger memories of varying sizes.

Multiple size memories in a programmable logic device

Growing community of inventors

Fremont, CA, United States of America

Srinivas T Reddy