The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 26, 2007

Filed:

Dec. 14, 2006
Applicants:

Richard G. Cliff, Los Altos, CA (US);

Srinivas T. Reddy, Fremont, CA (US);

Andy L. Lee, San Jose, CA (US);

David Lewis, Toronto, CA;

Inventors:

Richard G. Cliff, Los Altos, CA (US);

Srinivas T. Reddy, Fremont, CA (US);

Andy L. Lee, San Jose, CA (US);

David Lewis, Toronto, CA;

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/38 (2006.01); H03K 19/177 (2006.01);
U.S. Cl.
CPC ...
Abstract

Circuits, methods, and apparatus that provide integrated circuits having memories with multiple sizes. The memories may be dedicated embedded memories, or they may be distributed memories formed using memories or lookup tables in logic elements or other appropriate circuits. Configuration bits not needed by logic elements used for distributed memories can be used for data storage as well. These various memories may be combined or otherwise linked or chained together in different combinations to form larger memories of varying sizes.


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