Santa Clara, CA, United States of America

Srinivas Perisetty

This inventor holds 32 USPTO granted patents and 1 published patent application, primarily in Integrated Circuit Design. Top assignees: Altera Corporation, Atmel Corporation. Active years: 2005-2019.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Srinivas Perisetty. Retrieved from https://idiyas.com/inventor/srinivas-perisetty

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 32 (Patent Applications = 1)

% Patents Active = 46.9

Average Co-Inventor Count = 1.5

ph-index = 11

Forward Citations = 344(Granted Patents)

Location History:

San Jose, CA (US) (2005)
Hyderabad, IN (2013)
Santa Clara, CA (US) (2007 - 2019)

Company Filing History:

Years Active: 2005-2019

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Areas of Expertise:

Temperature Sensing

FPGA Performance

Power Management

Integrated Circuits

Memory Elements

Electrostatic Discharge

Voltage Regulation

Transistor Body Bias

Soft Error Immunity

Latch-Up Prevention

Flash Memory

Capacitor Protection

32 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 10200037 - Apparatus and methods for on-die temperature sensing to improve FPGA performance (2019-02-05),

2. 9735779 - Apparatus and methods for on-die temperature sensing to improve FPGA performance (2017-08-15),

3. 9496268 - Integrated circuits with asymmetric and stacked transistors (2016-11-15),

4. 8750026 - Integrated circuits with asymmetric and stacked transistors (2014-06-10),

5. 8732635 - Apparatus and methods for power management in integrated circuits (2014-05-20),

6. 8711614 - Memory elements with increased write margin and soft error upset immunity (2014-04-29),

7. 8618786 - Self-biased voltage regulation circuitry for memory (2013-12-31),

8. 8482963 - Integrated circuits with asymmetric and stacked transistors (2013-07-09),

9. 8369175 - Memory elements with voltage overstress protection (2013-02-05),

10. 8279660 - Static random-access memory with boosted voltages (2012-10-02),

11. 8099704 - Performance improvements in an integrated circuit by selectively applying forward bias voltages (2012-01-17),

12. 7990664 - Electrostatic discharge protection in a field programmable gate array (2011-08-02),

13. 7978450 - Electrostatic discharge protection circuitry (2011-07-12),

14. 7957177 - Static random-access memory with boosted voltages (2011-06-07),

15. 7920410 - Memory elements with increased write margin and soft error upset immunity (2011-04-05),

Title: The Innovative Journey of Srinivas Perisetty

Introduction:

Srinivas Perisetty, a visionary inventor based in Santa Clara, CA, has made significant contributions to the field of technology through his groundbreaking innovations.

Latest Patents:

Srinivas Perisetty's latest patents include cutting-edge solutions in artificial intelligence, machine learning, and renewable energy technologies, showcasing his commitment to driving progress in these crucial areas.

Career Highlights:

With a career spanning over two decades, Srinivas Perisetty has held key roles in leading tech companies, where he spearheaded research and development projects that have resulted in numerous successful patents and products. His expertise lies in translating complex ideas into practical solutions that have real-world impact.

Collaborations:

Throughout his career, Srinivas Perisetty has collaborated with top researchers, engineers, and industry experts to push the boundaries of innovation. His ability to work effectively in multidisciplinary teams has led to the development of cutting-edge technologies that have revolutionized the way we live and work.

Conclusion:

In conclusion, Srinivas Perisetty's relentless pursuit of innovation and his passion for creating solutions to global challenges have established him as a prominent figure in the world of technology. His work continues to inspire the next generation of inventors and entrepreneurs to push the boundaries of what is possible.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

1 patent pending: