The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 20, 2014
Filed:
Jul. 01, 2008
David Lewis, Toronto, CA;
Christopher F. Lane, San Jose, CA (US);
Sarathy Sribhashyam, San Jose, CA (US);
Srinivas Perisetty, Santa Clara, CA (US);
Tim Vanderhoek, Toronto, CA;
Vaughn Betz, Toronto, CA;
Thomas Yau-tsun Wong, Markham, CA;
Andy L. Lee, San Jose, CA (US);
David Lewis, Toronto, CA;
Christopher F. Lane, San Jose, CA (US);
Sarathy Sribhashyam, San Jose, CA (US);
Srinivas Perisetty, Santa Clara, CA (US);
Tim Vanderhoek, Toronto, CA;
Vaughn Betz, Toronto, CA;
Thomas Yau-Tsun Wong, Markham, CA;
Andy L. Lee, San Jose, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.