The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 02, 2011
Filed:
Dec. 14, 2006
Srinivas Perisetty, Santa Clara, CA (US);
Antonio Gallerano, Redwood City, CA (US);
Jeffrey T. Watt, Palo Alto, CA (US);
Cheng-hsiung Huang, Cupertino, CA (US);
Srinivas Perisetty, Santa Clara, CA (US);
Antonio Gallerano, Redwood City, CA (US);
Jeffrey T. Watt, Palo Alto, CA (US);
Cheng-Hsiung Huang, Cupertino, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
An ESD protection circuit is integrated into the core of an FPGA in a distributed fashion coupling the bodies of one or more transistors to the power supply pin and/or the ground pin of the FPGA. The ESD protection circuit includes one or more positive discharge paths and one or more negative discharge paths. In the case of a positive ESD event, the positive discharge paths are on and the negative discharge paths are off. In the case of a negative ESD event, the positive discharge paths are off and the negative discharge paths are on. In either event, the bodies of the transistors track the voltages at the power supply pin and/or the ground pin to protect the core from being by damaged by electrostatic discharge.