The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 05, 2013
Filed:
Sep. 01, 2010
Lin-shih Liu, Fremont, CA (US);
Andy L. Lee, San Jose, CA (US);
Ping-chen Liu, Fremont, CA (US);
Irfan Rahim, Milpitas, CA (US);
Srinivas Perisetty, Hyderabad, IN;
Lin-Shih Liu, Fremont, CA (US);
Andy L. Lee, San Jose, CA (US);
Ping-Chen Liu, Fremont, CA (US);
Irfan Rahim, Milpitas, CA (US);
Srinivas Perisetty, Hyderabad, IN;
Altera Corporation, San Jose, CA (US);
Abstract
Integrated circuits may include memory elements that are provided with voltage overstress protection. One suitable arrangement of a memory cell may include a latch with two cross-coupled inverters. Each of the two cross-coupled inverters may be coupled between first and second power supply lines and may include a transistor with a gate that is connected to a separate power supply line. Another suitable memory cell arrangement may include three cross-coupled circuits. Two of the three circuits may be powered by a first positive power supply line, while the remaining circuit may be powered by a second positive power supply line. These memory cells may be used to provide an elevated positive static control signal and a lowered ground static control signal to a corresponding pass gate. These memory cells may include access transistors and read buffer circuits that are used during read/write operations.