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For the Inventor, By the Inventor

Fremont, CA, United States of America

Soo-Young Oh

This inventor holds 8 USPTO granted patents. Top assignees: Hewlett-Packard Company, Ubitech, Inc., Ingenuus Corporation. Active years: 1993-2005.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Soo-Young Oh. Retrieved from https://idiyas.com/inventor/soo-young-oh-sf9lx8k5

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 8

% Patents Active = 87.5

Average Co-Inventor Count = 1.7

ph-index = 6

Forward Citations = 291(Granted Patents)


Company Filing History:

goldMedal3 out of 9,639 
 
Hewlett-Packard Company
 patents
silverMedal2 out of 2 
 
Ubitech, Inc.
 patents
bronzeMedal1 out of 1 
 
Ingenuus Corporation
 patent
4. 1 out of 834,601 
Other
 patents
where one patent can have more than one assignee

Years Active: 1993-2005

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8 patents (USPTO):Explore Patents
1. 6904581 - System and method for placement of dummy metal fills while preserving device matching and/or limiting capacitance increase (2005-06-07),
2. 6751785 - System and method for limiting increase in capacitance due to dummy metal fills utilized for improving planar profile uniformity (2004-06-15),
3. 6219631 - Method of generating R,C parameters corresponding to statistically worst case interconnect delays for computer simulation of integrated circuit designs (2001-04-17),
4. 6018623 - Method and system for determining statistically based worst-case on-chip (2000-01-25),
5. 5923568 - Distributed capacitance estimations of interconnects within integrated (1999-07-13),
6. 5610833 - Computer-aided design methods and apparatus for multilevel interconnect (1997-03-11),
7. 5231310 - Electrical and electronic appliance lock (1993-07-27),
8. D333632 - Unit for preventing the use of an electronic appliance during certain (1993-03-02),

Title: The Innovative Contributions of Soo-Young Oh

Introduction

Soo-Young Oh is a prominent inventor based in Fremont, CA, known for his significant contributions to the field of integrated circuit fabrication. With a total of 8 patents to his name, he has developed innovative systems and methods that enhance device matching and limit capacitance increases in semiconductor devices.

Latest Patents

One of his latest patents is a system and method for the placement of dummy metal fills while preserving device matching and limiting capacitance increase. This invention discloses a computer-automated method for locating dummy fills in an integrated circuit fabrication process. The method involves receiving an input layout of the integrated circuit and specifications for device matching. It locates dummy fills according to specific rules while ensuring that device matching is preserved. Additionally, it designates critical nets and identifies metal conductors, delineating exclusion zones to optimize the placement of dummy fills.

Another notable patent focuses on limiting capacitance increase due to dummy metal fills used to improve planar profile uniformity. This method also employs a computer-automated approach, reading layout files and designating critical nets. It identifies metal conductors and establishes exclusion zones to ensure that dummy fills are placed effectively without compromising the integrity of the circuit.

Career Highlights

Soo-Young Oh has worked with several reputable companies throughout his career, including Hewlett-Packard Company and Ubitech, Inc. His experience in these organizations has contributed to his expertise in integrated circuit design and fabrication.

Collaborations

Throughout his career, Soo-Young has collaborated with notable professionals in the field, including Norman H. Chang and Keh-Jeng Chang. These collaborations have further enriched his work and contributed to the advancement of technology in integrated circuits.

Conclusion

Soo-Young Oh's innovative patents and contributions to integrated circuit technology demonstrate his commitment to advancing the field. His work continues to influence the design and fabrication processes, ensuring improved performance and efficiency in semiconductor devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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