The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 25, 2000
Filed:
Oct. 10, 1997
Norman H Chang, Fremont, CA (US);
Valery Kanevsky, Los Gatos, CA (US);
O Sam Nakagawa, Redwood City, CA (US);
Soo-Young Oh, Fremont, CA (US);
Hewlett-Packard Company, Palo Alto, CA (US);
Abstract
A method and system of determining circuit performance-related characteristics, particularly delay and crosstalk, of interconnects includes defining a number of process variables which exhibit Gaussian distributions with respect to geometrical variances. A table of statistically based worst-case values representative of capacitances and resistances associated with different selections of the process variables is generated. In the preferred embodiment, the statistically based worst-case values are 3-sigma values. Also generated is a table of capacitance derivatives with respect to interconnect geometries. When a particular interconnect layout having selected process parameters is designated, the tables of 3-sigma values and derivatives are accessed to generate a resistance-capacitance (RC) net representative of the interconnect layout. The resistance and capacitance are correlated for each RC net and are partially determined by a randomized selection of values for geometries of the interconnect layout. The randomized selection of geometrical values is within the Gaussian distributions. Three-sigma delay and 3-sigma crosstalk may then be determined for the interconnect layout.