The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 17, 2001

Filed:

Jun. 09, 1999
Applicant:
Inventors:

Soo-Young Oh, Fremont, CA (US);

Won-Young Jung, Fremont, CA (US);

Assignee:

Ingenuus Corporation, Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract

A method of generating R,C parameters corresponding to statistically worst case interconnect delays for computer simulation of integrated circuit designs, comprising the steps of: computing a statistically worst case interconnect delay from randomly generated material and geometry values characterizing an integrated circuit interconnect process; computing a representative set of material and geometry values corresponding to the statistically worst case interconnect delay; and computing R,C parameters corresponding to the statistically worst case interconnect delay from the representative set of material and geometry values.


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Oh, Soo-Young. (2001). Method of generating r,c parameters corresponding to statistically worst case interconnect delays for computer simulation of integrated circuit designs (U.S. Patent No. 6219631). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6219631

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