Beaverton, OR, United States of America

Shuichi Sato

This inventor holds 4 USPTO granted patents. Top assignee: Tektronix, Inc.. Active years: 1980-1981.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Shuichi Sato. Retrieved from https://idiyas.com/inventor/shuichi-sato-noloh3lb

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 2.7

ph-index = 4

Forward Citations = 41(Granted Patents)


Company Filing History:


Years Active: 1980-1981

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4 patents (USPTO):Explore Patents

Title: The Innovations of Shuichi Sato

Introduction

Shuichi Sato is a prominent inventor based in Beaverton, OR (US). He has made significant contributions to the field of semiconductor technology, holding a total of 4 patents. His work focuses on improving the performance and efficiency of MOS transistors and complementary MOS devices.

Latest Patents

One of his latest patents is a method of manufacturing sub-micron channel width MOS transistors. This innovative method includes providing an oxygen-impermeable mask on a selected region of a semiconductor substrate. The process involves oxidizing the unmasked portion of the surface to create a thick oxide that is at least partially recessed in the substrate. This layer features a smoothly tapered beak that extends between the margin of the mask and the underlying silicon surface. After removing the mask, a selected impurity is implanted in the substrate beneath the selected region to form a thin impurity layer that terminates at a sloped portion of the substrate formed by the oxidation step.

Another notable patent is for an ultra high-speed complementary MOS device. This invention presents an improved, ultra high-speed (2GHz) CMOS inverter structure. It comprises a double-diffused, planar p-channel transistor and a nonplanar n-channel transistor formed within adjacent surface fields on the same substrate. The n-channel device includes a source region formed in an elevated plateau region on the substrate, along with a narrow, implanted channel-forming layer that extends through the plateau beneath the source region. This layer terminates at a slope joining the plateau to surrounding lower elevation portions of the substrate, with a drain region formed adjacent to the foot of the slope, spaced from the channel to provide a drift region between them.

Career Highlights

Shuichi Sato is currently employed at Tektronix, Inc., where he continues to innovate in the field of semiconductor technology. His work has had a significant impact on the development of high-performance electronic devices.

Collaborations

Throughout his career, Shuichi has collaborated with notable colleagues, including Tadanori Yamaguchi and Arthur D. Ritchie. These collaborations have contributed to the advancement of technology in their respective fields.

Conclusion

Shuichi Sato's contributions to semiconductor technology through his patents and work at Tektronix, Inc. highlight his role as a leading inventor in the industry. His

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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