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For the Inventor, By the Inventor

Wappingers Falls, NY, United States of America

Shaw-Ning Mei

USPTO Granted Patents = 13

Average Co-Inventor Count = 4.0

ph-index = 9

Forward Citations = 210(Granted Patents)


Location History:

  • Wappingers Falls, NY (US) (1993 - 1996)
  • Poughkeepsie, NY (US) (2000 - 2003)

Company Filing History:

goldMedal13 out of 164,197 
 
International Business Machines Corporation
 patents

Years Active: 1993-2003

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13 patents (USPTO):Explore Patents
1. 6541349 - Shallow trench isolation using non-conformal dielectric and planarizatrion (2003-04-01),
2. 6531265 - Method to planarize semiconductor surface (2003-03-11),
3. 6270353 - Low cost shallow trench isolation using non-conformal dielectric material (2001-08-07),
4. 6130453 - Flash memory structure with floating gate in vertical trench (2000-10-10),
5. 5521399 - Advanced silicon on oxide semiconductor device structure for BiCMOS (1996-05-28),
6. 5484738 - Method of forming silicon on oxide semiconductor device structure for (1996-01-16),
7. 5446312 - Vertical-gate CMOS compatible lateral bipolar transistor (1995-08-29),
8. 5394294 - Self protective decoupling capacitor structure (1995-02-28),
9. 5371022 - Method of forming a novel vertical-gate CMOS compatible lateral bipolar (1994-12-06),
10. 5341023 - Novel vertical-gate CMOS compatible lateral bipolar transistor (1994-08-23),
11. 5331199 - Bipolar transistor with reduced topography (1994-07-19),
12. 5279987 - Fabricating planar complementary patterned subcollectors with silicon (1994-01-18),
13. 5229322 - Method of making low resistance substrate or buried layer contact (1993-07-20),

Title: Shaw-Ning Mei: Innovator in Semiconductor Technology

Introduction

Shaw-Ning Mei is a prominent inventor based in Wappingers Falls, NY (US). He has made significant contributions to the field of semiconductor technology, holding a total of 13 patents. His innovative work has advanced the methods used in semiconductor fabrication, particularly in the areas of planarization and shallow trench isolation.

Latest Patents

Shaw-Ning Mei's latest patents include a method for shallow trench isolation using non-conformal dielectric and planarization. This method provides a way to planarize structures on a semiconductor substrate, which includes raised and lowered regions with vertical and horizontal surfaces. The process involves covering the upper regions with a masking layer of nitride and depositing filler material over the horizontal surfaces. The raised regions of the filler material are selectively removed in a single planarizing step, enhancing the efficiency of semiconductor manufacturing. Another notable patent describes a method to planarize a semiconductor surface using a Fence Creation and Elimination (FCE) process. This method involves filling shallow recesses on a semiconductor surface with a filling material and using a reverse mask to pattern the selectively etchable material, ultimately resulting in a planar semiconductor surface.

Career Highlights

Shaw-Ning Mei has had a distinguished career at the International Business Machines Corporation (IBM). His work has been instrumental in developing advanced semiconductor technologies that are crucial for modern electronics. His expertise in planarization techniques has positioned him as a leader in the field.

Collaborations

Shaw-Ning Mei has collaborated with notable colleagues such as Chang-Ming Hsieh and Louis L Hsu. These collaborations have further enriched his research and development efforts in semiconductor technology.

Conclusion

Shaw-Ning Mei's contributions to semiconductor technology through his innovative patents and collaborations have significantly impacted the industry. His work continues to influence advancements in semiconductor fabrication processes.

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