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For the Inventor, By the Inventor

Singapore, Singapore

See Hiong Leow

This inventor holds 14 USPTO granted patents and 29 published patent applications and 1 EPO patent. Top assignee: Micron Technology Incorporated. Active years: 2010-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: See Hiong Leow. Retrieved from https://idiyas.com/inventor/see-hiong-leow

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 14 

% Patents Active = 78.6

 

Average Co-Inventor Count = 2.5

ph-index = 3

Forward Citations = 86(Granted Patents)


Company Filing History:

goldMedal14 out of 39,222 
 
Micron Technology Incorporated
 patents

Years Active: 2010-2026

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14 patents (USPTO):Explore Patents
1. 12757414 - Bondable pillars for wire bonds in a semiconductor package (2026-10-06),
2. 12677696 - Semiconductor die assemblies with molded semiconductor dies and associated methods and systems (2026-07-07),
3. 12581976 - Wire bonding directly on exposed conductive vias and interconnects and related systems and methods (2026-03-17),
4. 12476216 - Wire bonding for stacked memory dies (2025-11-18),
5. 12463140 - Flexible interposer for semiconductor dies (2025-11-04),
6. 12412811 - Split via structure for semiconductor device packaging (2025-09-09),
7. 9324676 - Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices (2016-04-26),
8. 9147623 - Stacked microelectronic devices and methods for manufacturing stacked microelectronic devices (2015-09-29),
9. 8900923 - Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices (2014-12-02),
10. 8803307 - Stacked microelectronic devices and methods for manufacturing stacked microelectronic devices (2014-08-12),
11. 8501546 - Stacked microelectronic devices and methods for manufacturing stacked microelectronic devices (2013-08-06),
12. 8399971 - Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices (2013-03-19),
13. 8093702 - Stacked microelectronic devices and methods for manufacturing stacked microelectronic devices (2012-01-10),
14. 7741150 - Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices (2010-06-22),

Title: Innovations by See Hiong Leow

Introduction

See Hiong Leow is a prominent inventor based in Singapore, known for his significant contributions to the field of semiconductor technology. He holds a total of 14 patents, showcasing his expertise and innovative spirit in developing advanced solutions for memory systems.

Latest Patents

Among his latest patents is a method for wire bonding for stacked memory dies. This invention addresses the challenges associated with increasing wire lengths as the stack of memory dies grows. The method ensures that bonding multiple wires does not create gaps that could lead to short circuits between neighboring wires. Another notable patent involves a flexible interposer for semiconductor dies. This invention includes a semiconductor device assembly that features a flexible interposer, which enhances the arrangement and connectivity between stacked semiconductor dies.

Career Highlights

See Hiong Leow has made a significant impact in the semiconductor industry through his work at Micron Technology Incorporated. His innovative approaches have led to advancements in memory systems, making them more efficient and reliable.

Collaborations

He has collaborated with notable coworkers such as Edmund Koon Tian Lua and Choon Kuan Lee, contributing to various projects that push the boundaries of semiconductor technology.

Conclusion

See Hiong Leow's contributions to the field of semiconductor technology through his patents and collaborations highlight his role as a leading inventor in the industry. His work continues to influence advancements in memory systems and semiconductor devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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