The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2026

Filed:

Aug. 30, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Kelvin Tan Aik Boo, Singapore, SG;

Seng Kim Ye, Singapore, SG;

Hong Wan Ng, Singapore, SG;

Ling Pan, Singapore, SG;

See Hiong Leow, Singapore, SG;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/52 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 24/48 (2013.01); H01L 21/4857 (2013.01); H01L 21/486 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 25/0657 (2013.01); H01L 23/49816 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48235 (2013.01); H01L 2224/73215 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06562 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/3512 (2013.01);
Abstract

Stacked semiconductor devices, and related systems and methods, are disclosed herein. In some embodiments, the stacked semiconductor device includes a package substrate having at least a first layer and a second layer, an interconnect extending through the package substrate, a stack of dies carried by the package substrate, and one or more wirebonds electrically coupling the stack of dies to package substrate. Each of the layers of the package substrate can include a section of the interconnect with a frustoconical shape. Each of the sections can be directly coupled together. Further, the section in an uppermost layer of the package substrate is exposed at an upper surface of the package substrate. The wirebonds can be directly coupled to the exposed surface of the uppermost section.


Find Patent Forward Citations

Boo, Kelvin Tan Aik. (2026). Wire bonding directly on exposed conductive vias and interconnects and related systems and methods (U.S. Patent No. 12581976). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12581976

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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