Komatsu, Japan

Saya Shimomura

This inventor holds 20 USPTO granted patents and 2 published patent applications, primarily in Semiconductor Devices. Top assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation. Active years: 2017-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Saya Shimomura. Retrieved from https://idiyas.com/inventor/saya-shimomura

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 20 

% Patents Active = 100.0

Average Co-Inventor Count = 2.8

ph-index = 2

Forward Citations = 9(Granted Patents)


Location History:

  • Ishikawa, JP (2020)
  • Komatsu, JP (2020 - 2021)
  • Komatsu Ishikawa, JP (2017 - 2024)

Company Filing History:


Years Active: 2017-2026

Loading Chart...
Areas of Expertise:
MOSFET
Reverse Recovery
Field Plate Electrode
Trench-Gate
Power Semiconductor
Manufacturing Methods
Transistor
Electrode Design
Buried Field Plates
Device Characteristics
Semiconductor Technology
Peripheral Trench
20 patents (USPTO):Explore Patents

Title: Saya Shimomura: Innovator in Semiconductor Technology

Introduction

Saya Shimomura is a prominent inventor based in Komatsu, Ishikawa, Japan. She has made significant contributions to the field of semiconductor technology, holding a total of 20 patents. Her work has been instrumental in advancing the design and manufacturing processes of semiconductor devices.

Latest Patents

Among her latest patents is a semiconductor device and method for manufacturing the same. According to one embodiment, this semiconductor device includes first to third electrodes, a semiconductor member, a first conductive member, a connecting member, a first member, and an insulating member. The semiconductor member comprises first to third semiconductor regions, with the first semiconductor region positioned between the first electrode and the third semiconductor region. This region includes first to third partial regions, while the second semiconductor region is located between the first and third semiconductor regions, containing third and fourth semiconductor portions. The third semiconductor region consists of first and second semiconductor portions. The second electrode is electrically connected with the third semiconductor region, and the third electrode includes a first electrode portion. The first conductive member features first to third conductive regions, and the connecting member is electrically connected with the first conductive member. The first member is situated between the first electrode portion and the connecting member.

Another embodiment of her semiconductor device includes first and second electrodes, first to third semiconductor regions, a conductive body, and a gate electrode. The first semiconductor region is located on the first electrode and is electrically connected with it. The second semiconductor region is positioned on the first semiconductor region, while the third semiconductor region is located on a portion of the second semiconductor region. The conductive body is situated in the first semiconductor region with an insulating part interposed. A lower surface of the conductive body features first and second surfaces, and the gate electrode is located in the insulating part, facing the second semiconductor region via a gate insulating layer. The second electrode is placed on the second and third semiconductor regions and is electrically connected with them.

Career Highlights

Saya Shimomura has worked with notable companies in the technology sector, including Kabushiki Kaisha Toshiba and Toshiba Electronic Devices & Storage Corporation. Her experience in these organizations has allowed her to refine her skills and contribute to groundbreaking innovations in semiconductor technology.

Collaborations

Throughout her career, Saya has collaborated with esteemed colleagues, including Hiroaki Katou and Toshifumi Nishig

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…