Satoshi Tazawa

Title: Satoshi Tazawa: Semiconductor Topography Simulation Inventor.

Introduction

Satoshi Tazawa is an inventor associated with semiconductor process simulation and three-dimensional solids modeling. Based in Atsugi, Japan, he is credited with 7 patents. His work includes methods for modeling how etching and deposition processes change the surfaces of semiconductor wafers and other workpieces.

Latest Patents

**Boolean Trajectory Solid Surface Movement Method.** This method simulates changes to a workpiece’s topography as it undergoes process steps, including isotropic or anisotropic deposition and etching. It uses material solids to represent different materials on the workpiece and trajectory solids to drive their deformation through Boolean operations. The approach supports spatially varying process steps while helping avoid invalid self-intersecting surfaces and reducing small edges that can produce irregular surfaces.

**Surface Sweeping Method for Surface Movement in Three Dimensional.** This method deforms solids in a topography simulator while avoiding invalid self-intersecting structures. It represents a material surface as segments, constructs a solid for each segment, and applies Boolean set operations as the surface is swept. For processes involving simultaneous deposition and etching, separate temporary solids can be used for each process before producing the deformed solid.

Career Highlights

Tazawa’s listed company affiliations include Intel Corporation and Nippon Telegraph and Telephone Corporation. His patent work reflects an emphasis on computational techniques for representing material surfaces and simulating semiconductor manufacturing processes.

Collaborations

His listed coworkers include Francisco A. Leon and Akira Yoshii. The patent methods described above address challenges in three-dimensional modeling and process simulation.

Conclusion

Satoshi Tazawa’s inventions focus on reliable solids-modeling methods for simulating semiconductor topography, including surface movement during etching and deposition.