IDiyas

For the Inventor, By the Inventor

Kamakura, Japan

Satoru Tamada

USPTO Granted Patents = 12

Average Co-Inventor Count = 1.4

ph-index = 4

Forward Citations = 39(Granted Patents)


Location History:

  • Kanagawa, JP (2011)
  • Kamakura, JP (2010 - 2017)

Company Filing History:

goldMedal10 out of 37,905 
 
Micron Technology Incorporated
 patents
silverMedal2 out of 54,664 
 
Intel Corporation
 patents

Years Active: 2010-2017

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12 patents (USPTO):
1. 9536582 - Enable/disable of memory chunks during memory access (2017-01-03),
2. 9064578 - Enable/disable of memory chunks during memory access (2015-06-23),
3. 8576627 - Memory array with inverted data-lines pairs (2013-11-05),
4. 8422297 - Multi level inhibit scheme (2013-04-16),
5. 8243538 - Small unit internal verify read in a memory device (2012-08-14),
6. 8077532 - Small unit internal verify read in a memory device (2011-12-13),
7. 7983091 - Divided bitline flash memory array with local sense and signal transmission (2011-07-19),
8. 7983085 - Memory array with inverted data-line pairs (2011-07-19),
9. 7965548 - Systems and devices including memory resistant to program disturb and methods of using, making, and operating the same (2011-06-21),
10. 7864585 - Multi level inhibit scheme (2011-01-04),
11. 7835187 - Boosting seed voltage for a memory device (2010-11-16),
12. 7755939 - System and devices including memory resistant to program disturb and methods of using, making, and operating the same (2010-07-13),
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