The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 04, 2011

Filed:

Mar. 31, 2008
Applicant:

Satoru Tamada, Kamakura, JP;

Inventor:

Satoru Tamada, Kamakura, JP;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 7/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

Memory devices and methods are disclosed to facilitate utilization of a multi level inhibit programming scheme. In one such embodiment, isolated channel regions having boosted channel bias levels are formed across multiple memory cells and are created in part and maintained through capacitive coupling with word lines coupled to the memory cells and biased to predetermined bias levels. Methods of manipulation of isolated channel region bias levels through applied word line bias voltages affecting a program inhibit effect, for example, are also disclosed.


Find Patent Forward Citations

Tamada, Satoru. (2011). Multi level inhibit scheme (U.S. Patent No. 7864585). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7864585

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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