Robert J Palermo

Title: The Innovations of Robert J Palermo

Introduction

Robert J Palermo is a notable inventor based in Shoreview, MN (US). He has made significant contributions to the field of digital logic circuits and timing analysis, holding a total of 7 patents. His work has advanced the accuracy and efficiency of timing verification in complex electronic systems.

Latest Patents

One of his latest patents is titled "Transistor-level timing analysis using embedded simulation." This patent discloses a high accuracy method for transistor-level static timing analysis. Accurate static timing verification requires that individual gate and interconnect delays be accurately calculated. At the sub-micron level, calculating gate and interconnect delays using delay models can result in reduced accuracy. Instead, the proposed method calculates delays through numerical integration using an embedded circuit simulator. It takes into account short circuit current and carefully chooses the set of conditions that results in a tight upper bound of the worst-case delay for each gate. Similar repeating transistor configurations of gates in the circuit are automatically identified, and a novel interpolation-based caching scheme quickly computes gate delays from the delays of similar gates. A tight object code level integration with a commercial high-speed transistor-level circuit simulator allows efficient invocation of the simulation.

Another significant patent is "System and method for timing abstraction of digital logic circuits." This computer-implemented method abstracts the timing constraints for latches internal to a digital logic circuit, resulting in a clock characterization model. Timing information, such as propagation delays, set-up, and hold requirements for latches and combinational logic circuits contained in a digital logic circuit, are received, along with a description of a class of clock scheme for clocking the circuit. Clock parameters are selected for the clock scheme class. The internal timing constraints for the digital logic circuit are expressed as timing constraint expressions, which are a function of the clock parameters. The expressions are combined to define a region of feasible clock operation expressed in terms of the clock parameters.

Career Highlights

Throughout his career, Robert has worked with prominent companies such as Cadence Design Systems, Inc. and Unisys Corporation. His experience in these organizations has allowed him to refine his skills and contribute to groundbreaking innovations in the field of digital logic design.

Collaborations

Robert has collaborated with notable professionals in his field, including Mohammad S Mortazavi and Karem A Sakallah. These collaborations have further enriched his work and expanded the impact