The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 05, 2005
Filed:
Aug. 23, 2002
Robert J Palermo, Shoreview, MN (US);
Karem A. Sakallah, Ann Arbor, MN (US);
Shekaripuram V. Venkatesh, San Jose, CA (US);
Mohammad Mortazavi, Fremont, CA (US);
Robert J Palermo, Shoreview, MN (US);
Karem A. Sakallah, Ann Arbor, MN (US);
Shekaripuram V. Venkatesh, San Jose, CA (US);
Mohammad Mortazavi, Fremont, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
A computer-implemented method abstracts the timing constraints for latches internal to a digital logic circuit, resulting in a clock characterization model. Timing information (such as propagation delays, set-up and hold requirements) for latches and combinational logic circuits contained in a digital logic circuit are received, as is a description of a class of clock scheme for clocking the circuit. Clock parameters are selected for the clock scheme class. The internal timing constraints for the digital logic circuit are expressed as timing constraint expressions which are a function of the clock parameters. The expressions are combined to define a region of feasible clock operation expressed in terms of the clock parameters.