Karem A Sakallah

USPTO Granted Patents = 7 (Patent Applications = 1)

Average Co-Inventor Count = 3.4

ph-index = 5

Forward Citations = 58(Granted Patents)

Location History:

Ann Arbor, MN (US) (2005)
Ann Arbor, MI (US) (2002 - 2016)

Company Filing History:

4 out of 2,542

Cadence Design Systems, Inc.

patents

3 out of 3,370

University of Michigan

patents

Years Active: 2002-2016

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7 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 9389983 - Verification of complex systems that can be described by a finite state transition system (2016-07-12),

2. 8954909 - Automated scalable verification for hardware designs at the register transfer level (2015-02-10),

3. 8601414 - Automated scalable verification for hardware designs at the register transfer level (2013-12-03),

4. 7346872 - Functional timing analysis for characterization of virtual component blocks (2008-03-18),

5. 6877143 - System and method for timing abstraction of digital logic circuits (2005-04-05),

6. 6457159 - Functional timing analysis for characterization of virtual component blocks (2002-09-24),

7. 6442739 - System and method for timing abstraction of digital logic circuits (2002-08-27),

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1 patent pending:

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