Method of compacting data representations of hierarchical logic designs

Abstract

An automatic process of compacting or 'flattening' a hierarchical multi-level logic design for more efficient timing analysis purposes while using electronic design automation tools, the hierarchical multi-level logic design having at least one higher level logic design including at least one instance, but typically a plurality of instances, of a lower level logic design. The process includes creating a file for storing logic design data defining a lower level logic design and timing analysis input data for the lower level logic design, deleting selected logic design data from the file wherein the deleted data represents all internal paths and components of the lower level logic which are not connected to the higher level logic design, thereby leaving only data for external paths and components of the lower level logic design connected to the higher level logic design in the file. The file creation and internal path and component deletion steps are repeated for all lower level logic designs in the overall hierarchical multi-level logic design. Another file is created to hold the logic design data defining the higher level logic design and timing analysis input data for the higher level logic design. The modified logic design data and timing analysis data for the lower level logic designs in the lower level logic design files are automatically substituted into appropriate places in the file for the higher level logic design, thereby decreasing the size of the overall logic design data being processed for timing analysis purposes.