Logic timing analysis for multiple-clock designs

Abstract

A system and method for detecting timing design errors in a design having multiple state devices clocked by multiple clock signals. The design includes at least first and second state devices clocked by first and second clock signals. A reference time is designated, and a time differential between successive triggering edges of the first and second clock signals is calculated. The time of the occurrence of each triggering edge of the first and second clock signal is calculated with respect to the reference time, rather than directly with respect to each other. The calculation of the time differential includes storing a period time and a time offset the first and second clock signals. The time offsets are time durations measured from the reference time to the first pulse of each of the first and second clock signals that occur simultaneously with, or subsequent to, the reference time. The calculated time differential is then compared to the known, worst-case timing parameters to determine whether a timing error exists.