Robert F Pfeifer

Title: Innovations of Robert F. Pfeifer

Introduction

Robert F. Pfeifer is a notable inventor based in Centerville, OH (US). He has made significant contributions to the field of semiconductor technology, holding a total of 4 patents. His work primarily focuses on processes that enhance the reliability and efficiency of memory devices.

Latest Patents

Pfeifer's latest patents include the "Mixed dielectric process and nonvolatile memory device fabricated thereby." This innovative process fabricates volatile and nonvolatile field effect devices on a common semiconductor wafer. A unique feature of this process is the elimination of nitride from beneath any poly I layers while selectively retaining sandwiched and coextensive segments of nitride and poly II layers for the memory devices. The method begins with a wafer treated according to the general localized oxidation of silicon process, followed by a blanket enhancement implant and selectively masked depletion implants. The process continues with a contact etch step, deposition of a poly I layer, and a resistor forming implant. The subsequent steps involve growing a first isolation oxide, performing selective implants, and etching the memory area, which is then covered by a regrowth of a very thin memory oxide. The wafer is coated with nitride and poly II, followed by a patterned plasma etch that removes unwanted areas of poly II and nitride. This process enhances the reliability of the complete integrated circuit (IC).

Another significant patent is the "Unified CMOS/SNOS semiconductor fabrication process." This unified process allows for the fabrication of CMOS and SNOS devices on a common wafer. It significantly reduces the number of masking operations while limiting fabrication temperatures after the formation of the memory device dielectric. The process prescribes the formation of p and n-wells, gate oxides, and a patterned conductive poly layer. The source/drain regions in the respective wells are then doped to match the poly layer patterns. The operational characteristics of the SNOS device are refined, followed by the growth of a first isolation layer of silicon dioxide and the sequential formation of the memory dielectric. The process concludes with the formation of a second isolation oxide and a patterned layer of interconnect metal.

Career Highlights

Robert F. Pfeifer has had a distinguished career at NCR Corporation, where he has contributed to various innovative projects in semiconductor technology. His expertise in memory device fabrication has positioned him as a key figure in the industry.

Collaborations