Ncr Corporation

Robert F Pfeifer

Murray L Trudel

Raymond A Turi

Ronald W Brower

Roberto Romano-Moran

Samuel Y Chiao

John K Stewart, Jr

Edward H Honnigford

Vinod K Dham

A process for fabricating volatile and nonvolatile field effect devices on a common semiconductor wafer, and a unique composite structure for a nonvolatile memory device fabricated according to the process. A distinct feature of the process is the elimination of nitride from beneath any poly I layers while selectively retaining sandwiched and coextensive segments of nitride and poly II layers for the memory devices. In one form, the method commences with a wafer treated according to the general localized oxidation of silicon process, followed by a blanket enhancement implant and selectively masked depletion implants. The succeeding contact etch step is followed by a deposition of a poly I layer, a resistor forming implant and a patterned etch of the poly I layer. Thereafter, a first isolation oxide is grown, selective implants are performed to center the memory window, the memory area is etched, and the memory area is covered by a regrowth of a very thin memory oxide. The wafer is then coated with nitride and poly II, before undergoing a patterned plasma etch which successively and coextensively removes poly II and nitride in unwanted areas. Consequently, any nitride which remains is in a sandwiched arrangement with an overlying layer of poly II. The process inherently retains no nitride under any poly I layer, and thereby enhances the reliability of the complete IC. The composite nonvolatile memory device includes a poly II nonvolatile memory capacitor, a poly II depletion IGFET, and a poly I depletion IGFET over a single continuum of channel. The structural arrangement provides for selective access to the nonvolatile memory capacitor through the poly I IGFET during the write mode.

Mixed dielectric process and nonvolatile memory device fabricated thereby

A unified process for fabricating CMOS and SNOS devices on a common wafer. The process provides for the formation of poly resistors and interconnects at multiple levels while eliminating residual silicon nitride from active devices excepting the nonvolatile SNOS type memory cells. Foremost, the process significantly reduces the number of masking operations while limiting the fabrication temperatures at stages after the formation of the memory device dielectric. In the preferred arrangement, the process prescribes the formation of p and n-wells, gate oxides over the wells, and a patterned conductive poly layer thereupon. By alternate photoresist masking, the source/drain regions in the respective wells are then doped to coincide with the corresponding poly layer patterns. Thereafter, the SNOS device operational characteristics are refined, a first isolation layer of silicon dioxide is grown, and the memory dielectric is sequentially formed. Following the deposition of another conductive poly layer, this layer and the underlying silicon nitride from the memory dielectric are together selectively etched to retain the second layer of poly only at interconnect locations, resistors and the SNOS devices. Fabrication is concluded with the formation of a second isolation oxide and a patterned layer of interconnect metal.

Unified CMOS/SNOS semiconductor fabrication process

Disclosed is a process for forming self-aligned polysilicon gates and interconnecting conductors having a single conductivity and single impurity type in CMOS integrated circuits. After forming a polysilicon layer over the gate oxide, the polysilicon is doped with n-type impurities. Next, the polysilicon is covered with a relatively thick oxide serving as an implantation mask and then patterned into gates and conductors. Finally, by using ion implantation sources and drains for the p-FET and n-FET are formed in a self-aligned relationship with the corresponding gates.

Polysilicon-doped-first CMOS process

Disclosed is a process for a CMOS integrated circuit having polysilicon conductors of a single conductivity, single impurity type. After forming the conductors they are covered by an oxidation and diffusion mask consisting of a dual layer of silicon dioxide and silicon nitride. Then, source and drains of the p-channel and n-channel transistors are formed. Next, an implantation or diffusion barrier is grown over sources and drains. The oxidation and diffusion mask over all the conductors is then removed and they are all doped simultaneously using a single type impurity. The process may be used to additionally form polysilicon resistors by initially doping the polysilicon to a low level of conductivity. After forming the conductors and resistors they are covered by the oxidation and diffusion mask. Then a resistor mask of either silicon nitride or polysilicon is formed over the resistors to protect them during the high conductivity doping of the conductors.

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Centerville, OH, United States of America

Robert F Pfeifer