Unified cmos/snos semiconductor fabrication process

Abstract

A unified process for fabricating CMOS and SNOS devices on a common wafer. The process provides for the formation of poly resistors and interconnects at multiple levels while eliminating residual silicon nitride from active devices excepting the nonvolatile SNOS type memory cells. Foremost, the process significantly reduces the number of masking operations while limiting the fabrication temperatures at stages after the formation of the memory device dielectric. In the preferred arrangement, the process prescribes the formation of p and n-wells, gate oxides over the wells, and a patterned conductive poly layer thereupon. By alternate photoresist masking, the source/drain regions in the respective wells are then doped to coincide with the corresponding poly layer patterns. Thereafter, the SNOS device operational characteristics are refined, a first isolation layer of silicon dioxide is grown, and the memory dielectric is sequentially formed. Following the deposition of another conductive poly layer, this layer and the underlying silicon nitride from the memory dielectric are together selectively etched to retain the second layer of poly only at interconnect locations, resistors and the SNOS devices. Fabrication is concluded with the formation of a second isolation oxide and a patterned layer of interconnect metal.