The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 27, 1983
Filed:
Dec. 18, 1981
Ronald W Brower, Kettering, OH (US);
Samuel Y Chiao, West Carrollton, OH (US);
Robert F Pfeifer, Centerville, OH (US);
Roberto Romano-Moran, Centerville, OH (US);
NCR Corporation, Dayton, OH (US);
Abstract
Disclosed is a process for forming self-aligned polysilicon gates and interconnecting conductors having a single conductivity and single impurity type in CMOS integrated circuits. After forming a polysilicon layer over the gate oxide, the polysilicon is doped with n-type impurities. Next, the polysilicon is covered with a relatively thick oxide serving as an implantation mask and then patterned into gates and conductors. Finally, by using ion implantation sources and drains for the p-FET and n-FET are formed in a self-aligned relationship with the corresponding gates.