Richard Frank Rizzolo

This inventor holds 18 USPTO granted patents and 1 published patent application. Top assignees: International Business Machines Corporation, Cadence Design Systems, Inc.. Active years: 1988-2022.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Richard Frank Rizzolo. Retrieved from https://idiyas.com/inventor/richard-frank-rizzolo

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 18 (Patent Applications = 1)

% Patents Active = 61.1

Average Co-Inventor Count = 4.2

ph-index = 9

Forward Citations = 203(Granted Patents)

Location History:

Poughkeepsie, NY (US) (2017)
Red Hook, NY (US) (1988 - 2022)

Company Filing History:

17 out of 166,351

International Business Machines Corporation

patents

1 out of 2,619

Cadence Design Systems, Inc.

patents

Years Active: 1988-2022

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18 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 11501047 - Error injection for timing margin protection and frequency closure (2022-11-15),

2. 11105853 - Empirical LBIST latch switching and state probability determination (2021-08-31),

3. 10048734 - Adaptive power capping in a chip (2018-08-14),

4. 9874917 - Adaptive power capping in a chip (2018-01-23),

5. 9733685 - Temperature-aware microprocessor voltage management (2017-08-15),

6. 9575529 - Voltage droop reduction in a processor (2017-02-21),

7. 7650535 - Array delete mechanisms for shipping a microprocessor with defective arrays (2010-01-19),

8. 6971054 - Method and system for determining repeatable yield detractors of integrated circuits (2005-11-29),

9. 6751765 - Method and system for determining repeatable yield detractors of integrated circuits (2004-06-15),

10. 6728914 - Random path delay testing methodology (2004-04-27),

11. 6662324 - Global transition scan based AC method (2003-12-09),

12. 6532571 - Method to improve a testability analysis of a hierarchical design (2003-03-11),

13. 6490702 - Scan structure for improving transition fault coverage and scan diagnostics (2002-12-03),

14. 6453436 - Method and apparatus for improving transition fault testability of semiconductor chips (2002-09-17),

15. 6442720 - Technique to decrease the exposure time of infrared imaging of semiconductor chips for failure analysis (2002-08-27),

Title: Richard Frank Rizzolo: A Pioneer in Innovation

Introduction: Richard Frank Rizzolo, a visionary inventor based in Red Hook, NY, is an embodiment of creativity and dedication in the realm of technology and innovation. With an impressive portfolio of 18 patents, his groundbreaking work continues to inspire the next generation of inventors.

Latest Patents: Among his latest patents is the "Error Injection for Timing Margin Protection and Frequency Closure" method. This computer-implemented approach involves error injection and timing margin protection, showcasing his expertise in tackling complex technical challenges. Additionally, his "Empirical LBIST Latch Switching and State Probability Determination" method demonstrates his innovative solutions for logic built-in self-tests.

Career Highlights: Richard has made significant contributions to renowned companies such as IBM and Cadence Design Systems, Inc. His tenure at these organizations has been marked by his passion for pushing the boundaries of technology and driving innovation forward.

Collaborations: Throughout his career, Richard has collaborated with esteemed professionals like Franco Motika and Peilin Song. These collaborations have not only enhanced his own work but have also led to groundbreaking advancements in the field of technology.

Conclusion: Richard Frank Rizzolo's unwavering commitment to innovation and his exceptional creativity have solidified his status as a pioneer in the world of inventors. His impact is felt not only through his numerous patents but also through his influence on the next generation of innovators who continue to be inspired by his remarkable achievements.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

1 patent pending: