The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 11, 2003

Filed:

Jan. 21, 2000
Applicant:
Inventors:

Richard M. Gabrielson, Vestal, NY (US);

Kevin W. McCauley, Greene, NY (US);

Richard F. Rizzolo, Red Hook, NY (US);

Bryan J. Robbins, Poughkeepsie, NY (US);

Joseph M. Swenton, Owego, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ; G01R 3/128 ;
U.S. Cl.
CPC ...
G06F 1/750 ; G01R 3/128 ;
Abstract

A method to improve the testability and analysis of a hierarchical semiconductor chip design formed from a plurality of macros, each macro identifying a particular portion of a semiconductor chip design. This method includes providing a first macro netlist that identifies a logical description of a first portion of the semiconductor chip design and performing RPT analysis on the first macro netlist. The method also includes providing a second macro netlist identifying a logical description of a second portion of the semiconductor chip design and performing an RPT analysis on the second macro netlist. The first macro netlist is combined with the second macro netlist and an RPT analysis is performed on the combination of the first and second macro netlists.


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