Austin, TX, United States of America

Ravi T Jotwani

This inventor holds 3 USPTO granted patents and 1 published patent application. Top assignee: Advanced Micro Devices Corporation. Active years: 2000-2019.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Ravi T Jotwani. Retrieved from https://idiyas.com/inventor/ravi-t-jotwani

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 3 

% Patents Active = 100.0

Average Co-Inventor Count = 2.3

ph-index = 2

Forward Citations = 58(Granted Patents)


Company Filing History:


Years Active: 2000-2019

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3 patents (USPTO):Explore Patents

Title: Innovations of Ravi T Jotwani

Introduction

Ravi T Jotwani is a notable inventor based in Austin, TX (US). He has made significant contributions to the field of memory operation and dynamic logic circuits. With a total of 3 patents to his name, Jotwani's work reflects a commitment to enhancing technology in computing systems.

Latest Patents

One of his latest patents is titled "Programmable write word line boost for low voltage memory operation." This invention describes a system and method for efficient power, performance, and stability tradeoffs of memory accesses under various conditions. The system management unit in a computing system interfaces with both memory and processing units, utilizing boosting of word line voltage levels to assist write operations. The computing system allows for the selection of multiple word line boost values, each associated with a specific cross-over region. This cross-over region defines a range of operating voltages for the memory, which helps determine whether to enable or disable the boosting of word line voltage levels based on a target operational voltage.

Another significant patent is "Dynamic logic circuit with device to prevent contention between pull-up and pull-down device." This circuit includes a precharge circuit designed to pull a dynamic node toward a voltage present on the voltage supply node during a precharge phase. During the evaluation phase, the evaluation circuit pulls the dynamic node toward a ground voltage based on a first input condition while inhibiting the pull-down response to a second input condition. The circuit features a pull-up circuit that includes first and second pull-up transistors, with the first activating during the precharge phase and the second activating after a delay during the evaluation phase.

Career Highlights

Ravi T Jotwani is currently employed at Advanced Micro Devices Corporation, where he continues to innovate and contribute to advancements in technology. His work has been instrumental in developing systems that enhance the efficiency and performance of memory operations.

Collaborations

Throughout his career, Jotwani has collaborated with notable colleagues, including Stephen Victor Kosonocky and Karthik Natarajan. These collaborations have further enriched his contributions to the field.

Conclusion

Ravi T Jotwani's innovative patents and contributions to the field of memory operation and dynamic logic circuits highlight his expertise and commitment to advancing technology. His work at Advanced Micro Devices Corporation continues to influence the industry positively.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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