Dynamic logic circuit with device to prevent contention between pull-up and pull-down device

Abstract

A circuit including is disclosed. The circuit includes a precharge circuit configured to pull a dynamic node toward a voltage present on the voltage supply node during a precharge phase, and an evaluation circuit configured to, during an evaluation phase, pull the dynamic node toward a ground voltage responsive to a first input condition and configured to inhibit pulling of the dynamic node down responsive to a second input condition. A pull-up circuit coupled between the first dynamic node and the voltage supply node includes first and second pull-up transistors. The first pull-up transistor is configured to activate responsive to the precharge phase. The second pull-up transistor is configured to activate at a delay time subsequent to entry of the evaluation phase. When the first and second pull-up transistors are active, a pull-up path is provided between the dynamic node and the voltage supply node.