The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 30, 2019

Filed:

Feb. 03, 2017
Applicant:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Inventors:

Alexander W. Schaefer, Austin, TX (US);

Ravi T. Jotwani, Austin, TX (US);

Samiul Haque Khan, Austin, TX (US);

David Hugh McIntyre, Sunnyvale, CA (US);

Stephen Victor Kosonocky, Ft. Collins, CO (US);

John J. Wuu, Fort Collins, CO (US);

Russell Schreiber, Austin, TX (US);

Assignee:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/08 (2006.01); G11C 11/418 (2006.01); G11C 5/14 (2006.01); G11C 11/413 (2006.01); G11C 11/419 (2006.01);
U.S. Cl.
CPC ...
G11C 8/08 (2013.01); G11C 5/145 (2013.01); G11C 11/413 (2013.01); G11C 11/418 (2013.01); G11C 11/419 (2013.01);
Abstract

A system and method for efficient power, performance and stability tradeoffs of memory accesses under a variety of conditions are described. A system management unit in a computing system interfaces with a memory and a processing unit, and uses boosting of word line voltage levels in the memory to assist write operations. The computing system supports selecting one of multiple word line boost values, each with an associated cross-over region. A cross-over region is a range of operating voltages for the memory used for determining whether to enable or disable boosting of word line voltage levels in the memory. The system management unit selects between enabling and disabling the boosting of word line voltage levels based on a target operational voltage for the memory and the cross-over region prior to updating the operating parameters of the memory to include the target operational voltage.


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