Advanced Micro Devices Corporation

Ravi T Jotwani

Stephen Victor Kosonocky

John J Wuu

Russell J Schreiber

Spencer Montgomery Gold

David Hugh McIntyre

Karthik Natarajan

Alexander W Schaefer

Michael C Braganza

Samiul Haque Khan

Giridhar Narayanaswami

A system and method for efficient power, performance and stability tradeoffs of memory accesses under a variety of conditions are described. A system management unit in a computing system interfaces with a memory and a processing unit, and uses boosting of word line voltage levels in the memory to assist write operations. The computing system supports selecting one of multiple word line boost values, each with an associated cross-over region. A cross-over region is a range of operating voltages for the memory used for determining whether to enable or disable boosting of word line voltage levels in the memory. The system management unit selects between enabling and disabling the boosting of word line voltage levels based on a target operational voltage for the memory and the cross-over region prior to updating the operating parameters of the memory to include the target operational voltage.

Programmable write word line boost for low voltage memory operation

A circuit including is disclosed. The circuit includes a precharge circuit configured to pull a dynamic node toward a voltage present on the voltage supply node during a precharge phase, and an evaluation circuit configured to, during an evaluation phase, pull the dynamic node toward a ground voltage responsive to a first input condition and configured to inhibit pulling of the dynamic node down responsive to a second input condition. A pull-up circuit coupled between the first dynamic node and the voltage supply node includes first and second pull-up transistors. The first pull-up transistor is configured to activate responsive to the precharge phase. The second pull-up transistor is configured to activate at a delay time subsequent to entry of the evaluation phase. When the first and second pull-up transistors are active, a pull-up path is provided between the dynamic node and the voltage supply node.

Dynamic logic circuit with device to prevent contention between pull-up and pull-down device

A buffer circuit includes a buffer input, a memory, a memory controller and an upper buffer limit register. The memory is coupled to receive information from the buffer input. The memory has a single-port for accessing a plurality of storage locations for storing the information. The upper buffer limit register is for storing an upper buffer limit value. The memory controller is coupled to the memory and the upper buffer limit register. The memory controller prioritizes writes over reads when the number of storage locations of the memory storing the information is less than the upper buffer limit value. The memory controller prioritizes reads over writes when the number of storage locations storing the information is greater than the upper buffer limit value.

Single-port trace buffer architecture with overflow reduction

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Austin, TX, United States of America

Ravi T Jotwani