San Jose, CA, United States of America

Rajvinder S Klair

This inventor holds 5 USPTO granted patents and 1 published patent application. Top assignee: Xilinx, Inc.. Active years: 2017-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Rajvinder S Klair. Retrieved from https://idiyas.com/inventor/rajvinder-s-klair

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 5 

% Patents Active = 80.0

Average Co-Inventor Count = 4.9

ph-index = 1

Forward Citations = 4(Granted Patents)


Company Filing History:


Years Active: 2017-2026

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5 patents (USPTO):Explore Patents

Title: Rajvinder S Klair: Innovator in Electronic Design Verification

Introduction

Rajvinder S Klair is a notable inventor based in San Jose, CA, who has made significant contributions to the field of electronic design verification. With a total of 5 patents to his name, Klair has developed innovative solutions that enhance the efficiency and accuracy of circuit design testing.

Latest Patents

One of Klair's latest patents is titled "Testbench for Sub-Design Verification." This invention involves the creation of a testbench that facilitates the verification of sub-designs within a larger circuit design. The process includes receiving a selection of a sub-design, generating a list of port-level signal information, and logging the switching activity of each signal during testing. This method ultimately leads to the generation of a sub-design testbench tailored for the selected sub-design.

Another significant patent is "Hierarchical Access Simulation for Signaling with More Than Two State Values." This method allows for the instantiation of a simulation of an electronic design for a device under test (DUT). It identifies a subset of leaf nodes with input/output signaling of more than two values and generates a bypass module to facilitate communication between the testbench and these nodes. This innovation streamlines the testing process and improves the overall functionality of electronic designs.

Career Highlights

Rajvinder S Klair is currently employed at Xilinx, Inc., a leading company in the field of programmable logic devices. His work at Xilinx has allowed him to apply his expertise in electronic design and contribute to the development of advanced verification methodologies.

Collaborations

Throughout his career, Klair has collaborated with talented professionals, including Dhiraj Kumar Prasad and Saikat Bandyopadhyay. These collaborations have fostered a creative environment that encourages innovation and the sharing of ideas.

Conclusion

Rajvinder S Klair is a distinguished inventor whose work in electronic design verification has led to the development of impactful patents. His contributions continue to shape the future of circuit design testing and verification.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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