The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 03, 2023
Filed:
Sep. 08, 2020
Xilinx, Inc., San Jose, CA (US);
Saikat Bandyopadhyay, San Jose, CA (US);
Rajvinder S. Klair, San Jose, CA (US);
Dhiraj Kumar Prasad, Hyderabad, IN;
Ender Tunc Eroglu, San Jose, CA (US);
Rupendra Bakoliya, Hyderabad, IN;
Jayashree Rangarajan, Los Altos Hills, CA (US);
XILINX, INC., San Jose, CA (US);
Abstract
A method includes instantiating a simulation of an electronic design for a device under test (DUT) in hardware design language responsive to a user selection thereof. A subset of leaf nodes from a plurality of leaf nodes from the electronic design with input/output signaling of more than two values is identified. A hierarchical path for each leaf node of the plurality of leaf nodes of the electronic design for the DUT with respect to a testbench is calculated. A bypass module for the subset of leaf nodes is generated. The bypass module is generated in response to detecting presence of the subset of leaf nodes in the electronic design with input/output signaling of more than two values. The bypass module facilitates communication between the testbench and the subset of leaf nodes. Leaf nodes other than the subset of leaf nodes communicate with the testbench without communicating through the bypass module.