The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2026

Filed:

Oct. 25, 2022
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Rajvinder S. Klair, San Jose, CA (US);

Saikat Bandyopadhyay, San Jose, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/33 (2020.01); G06F 30/31 (2020.01); G06F 111/20 (2020.01);
U.S. Cl.
CPC ...
G06F 30/33 (2020.01); G06F 30/31 (2020.01); G06F 2111/20 (2020.01);
Abstract

An adaptable framework for circuit design simulation verification generates a simulation database for a circuit design and processed design data for the circuit design. The processed design data includes source files for the circuit design referenced by the simulation database. The simulation database and the processed design data are exported from a host integrated development environment (IDE). A template writer configured to generate a simulation script for the circuit design using the simulation database is provided. The simulation script is generated by executing the template writer. The simulation script is generated according to one or more user-specified parameters of the template writer using the simulation database and the processed design data as exported.


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