The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 08, 2025
Filed:
Feb. 04, 2022
Xilinx, Inc., San Jose, CA (US);
Rajvinder S. Klair, San Jose, CA (US);
Dhiraj Kumar Prasad, Hyderabad, IN;
Saikat Bandyopadhyay, San Jose, CA (US);
Ashish Kumar Jain, Hyderabad, IN;
Shiyao Ge, San Jose, CA (US);
Tapodyuti Mandal, Hyderabad, IN;
Miti Joshi, Hyderabad, IN;
Xilinx, Inc., San Jose, CA (US);
Abstract
Testbench creation for sub-design verification can include receiving, using computer hardware, a selection of a sub-design of a circuit design. The sub-design is one of a plurality of sub-designs of the circuit design. The circuit design includes a plurality of parameter values. A list of port-level signal information is generated for the selected sub-design. The one or more parameter values of the circuit design are extracted. Switching activity of each port-level signal from the list is logged in a switching activity file while running a circuit design testbench for the circuit design with the selected sub-design in scope. From the list, the switching activity, and the one or more parameter values, a sub-design testbench for the selected sub-design is generated.