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For the Inventor, By the Inventor

Castro Valley, CA, United States of America

Qing K Zhu

This inventor holds 7 USPTO granted patents and 2 published patent applications. Top assignee: Intel Corporation. Active years: 1998-2002.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Qing K Zhu. Retrieved from https://idiyas.com/inventor/qing-k-zhu

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 7 

% Patents Active = 100.0

Average Co-Inventor Count = 1.2

ph-index = 6

Forward Citations = 126(Granted Patents)


Location History:

  • Freemont, CA (US) (1998)
  • Fremont, CA (US) (1998 - 1999)
  • Castro Valley, CA (US) (2000 - 2002)

Company Filing History:

goldMedal7 out of 56,365 
 
Intel Corporation
 patents

Years Active: 1998-2002

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7 patents (USPTO):Explore Patents
1. 6446016 - Sizing and insertion of decoupling capacitance (2002-09-03),
2. 6037801 - Method and apparatus for clocking a sequential logic circuit (2000-03-14),
3. 5866924 - Method and apparatus for routing a clock tree in an integrated circuit (1999-02-02),
4. 5850157 - Low voltage swing circuits for low power clock distribution and methods (1998-12-15),
5. 5849610 - Method for constructing a planar equal path length clock tree (1998-12-15),
6. 5786630 - Multi-layer C4 flip-chip substrate (1998-07-28),
7. 5717229 - Method and apparatus for routing a clock tree in an integrated circuit (1998-02-10),

Title: Innovations of Qing K Zhu

Introduction

Qing K Zhu is a notable inventor based in Castro Valley, CA (US). She has made significant contributions to the field of electrical engineering, particularly in power grid optimization and sequential logic circuits. With a total of 7 patents to her name, her work has had a profound impact on the industry.

Latest Patents

One of her latest patents is titled "Sizing and insertion of decoupling capacitance." This invention provides a method and apparatus for allocating decoupling capacitance in a power grid. The process involves evaluating a power grid model of an RLC network to identify power nodes with peak voltages that exceed specified thresholds. For each noisy node that violates these thresholds, a decoupling capacitor is inserted, and the power grid is re-evaluated. This iterative process continues until all power nodes meet the noise budget requirements.

Another significant patent is "Method and apparatus for clocking a sequential logic circuit." This invention describes a sequential logic circuit with data signal bistable elements that are clocked by qualified clocks. These qualified clocks are generated by AND gates, ensuring that the bistable elements are only clocked when valid data is present. This innovation leads to a substantial reduction in power consumption for the sequential logic circuit.

Career Highlights

Qing K Zhu is currently employed at Intel Corporation, where she continues to innovate and develop new technologies. Her work at Intel has positioned her as a key player in advancing electrical engineering solutions.

Collaborations

Throughout her career, Qing has collaborated with notable colleagues, including Ameet S Bhansali and Michael Yimin Zhang. These collaborations have further enhanced her contributions to the field.

Conclusion

Qing K Zhu's innovative patents and her work at Intel Corporation highlight her significant role in the advancement of electrical engineering. Her contributions continue to shape the future of technology and power management.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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